Maximus Z690 and Alder Lake: Modern CPU's require Modern Overclocking Solutions.

[Falkentyne]

Asus Z690, Maximus series and Alder Lake: The best tools for the best FPS.

 

First, let me start by thanking Shamino @ ROG Asus for allowing me and the other testers to put this exciting new hardware through its paces and experiment with the new overclocking features and architecture changes, and for the hard work to get these boards running well with these new features.

Also I need to thank cstkl1 and RobertoSampiao for helping me write this. Without their help, I would never have been able to do this.
And VERY BIG thank you to Skatterbencher for his excellent, precise, clear cut youtube videos on explaining these features and helping me with this guide.

 

Disclaimer ! These settings and methods were tested on *ENGINEERING* Qualification Sample CPU's ("QS") and
pre-production boards, so it is possible that some features may perform differently, slightly differently
identically, or even not work at all on retail CPU's. While QS samples tend to reflect final retail hardware, there may still be undocumented differences, errata, thermal issues or features that may be present or not present on retail parts.

 

AVX-512 support is available with Asus boards! Some of you may really love this but I am not sure if AVX512 was intended or QA'd by Intel, VRM limits may not be set for high OCP limits with AVX512. I encountered OCP with AVX512 at 5.2 ghz, so if you encounter it, you can change CPU Current Capacity in Digi+VRM.

To use AVX-512, please disable all of the E-cores. The AVX512 offsets and clipping are available just like they were and described in the Rocket Lake Z590 guide.

 

*MEMORY STUFF and DDR5*

 

DDR5 operates in 2x32 bit mode rather than 1x64 bit mode. Power management (PMIC) has also been moved from the motherboard to the memory, so the memory itself manages the voltages.

The new changes to the bank structure means that two sticks of DDR5 are operating in the equivalent of "Quad channel" mode when compared to DDR4. DDR4 and DDR5 memory should no longer be compared on an apples to apples level due to the number of changes.

There are two channels per dimm and two memory controllers on the DDR5 side so the dims operate in quad channel mode for 2 sticks. CAS latency seems to have a lesser effect on latency on DDR5 than 4, for example. Max Trefi can go up to 262k, but there is no noticeable benefit from going higher than 65535, and a lot of risk of increasing stability problems with high heat. TRCD/TRP can now be set separately, focus on these for your overclocks, as well as the subs.

 

Yeeted tREFI may also risk an instant BSOD when you stop a stress test when the memory heats up or when you use sleep mode.
PMIC defaults to 1.10v for VDD and VDDQ. Some memory modules may want up to 50m-100mv higher VDDQ than VDD when overclocking. A "high voltage" mode allows higher than 1.43v, however this is an actual register toggle within the memory itself. Some modules are not compatible with this register, so enabling it will just reset the voltage back to default, or prevent booting at all. More accurately it uses a target voltage based on 10mv resolution calculation rather than 5mv, which means the real voltage will be much lower than what you think you set, if you are using incompatible sticks.

PMIC voltages's are usually synched together per channel but can be set separately both per channel AND per Dimm. There are three switching rails, VDD, VDDQ and VPP. VCCSA (System Agent) is still there. I have been unable to test changing this as my Micron sticks do not go much higher than 5200 XMP (5600 did work with a lot of difficulty).

Power rails have been simplified on the motherboard. There are two master rails, VCCIA and VCCAUX (sorry I don’t remember the exact names). IA rail controls Vcore and vGPU. AUX rail controls everything else (SA, FIVR, etc).
PMIC is on the memory which controls the voltage the memory actually runs at (VDDQ, VDD etc).
This is sourced from the motherboard’s 5V supply. As mentioned above, some modules have a high voltage bit which can allow more than 1.435v.

Secure Pmic mode: cannot be adjusted in windows. Allows up to 1.435v. Compatible with all 5mv resolution
OC Pmic: can be adjusted in windows. Can set yeet volts up to 2.070v. 10mv resolution

 

===================

 

Some values available in BIOS and should you care:

 

SPD Hub VLDO (1.8v): Don’t bother
SPD Hub (VDDIO) (1.0v): Don’t bother
Memory VDD voltage (definitely use it. 1.25v+ is good for OC)
Memory VDDQ voltage (1.2.5v+ is good for OC)
Memory VDDP voltage: Don’t bother.
Memory switching freq: not much help.
Memory current capacity: not really needed
System Agent: 1.25v+ (ask cstkl1 about this, there seem to be some issues with high system agent and some memory settings
Memory controller voltage (external): 1.25v+ for OC
Transmitter VDDQ (max to any high limit VDD, VDDQ).

So tl;dr: concern yourself with vdd, vddq, VCCSA, MC VDD, TX VDDQ.

 

===========
ROG Shamino’s rule of memory voltages:
===========

 

Typically the higher the density, the lower the V tolerance, eg, V for 4*DR< V for 2*DR <V for 4*SR< V for 2*SR.

 

Micron sticks:
SR modules typically can scale with VDDQ>1.35v while VDD may fail training >1.35v. So you may end up running something like 1.35v VDD + 1.435v VDDQ. SR module also like VDDQ to be ~ 50++mv-100mv higher than VDD so try to OV them asynch.

DR modules may have less V tolerance, so something like 1.25v VDD + 1.35v VDDQ will be what you end up maxing out at.
Some micron sticks may end up MORE stable fully loaded than idle. Be careful about idle BSOD’s. This may get worse if you start yeeting tREFI and end up BSOD’ing at the very end of a stress test.

1T Command rate will NOT work.

 

Hynix sticks:
SR modules typically can scale with VDD>1.3v while VDDQ may not need much over 1.25v. So you may end up running something like 1.35v VDDQ + 1.25v VDDQ. (inverse from what you see on micron) Similar for DR modules.
1.25v MC VDD works well for them. 1T command rate works with these.

 

Samsung Sticks:
Yes. Don’t need to say more.
Some modules do not like >1.25v Memory controller VDD, while some need it to scale for high frequencies.
You also need to scale the TX VDDQ according to VDD/VDDQ levels. A rule of thumb is to set it to the highest of either your VDD or VDDQ but try to not exceed 1.6v. Sometimes the FIVR rail will trip on you if you do.

 

Shamino’s rule:

For starters, you can just run 1.25v on both VDD and VDDQ for Hynix, 1.25VDD+1.35VDDQ for Micron, and 1.35VDD+1.35VDDQ for Samsung and let the BIOS decide on the rest for you by leaving them auto. You may also want to start with Asus Memory Presets.

Another strategy worth trying is:
Synch DRAM VDD with MC VDD, Synch TX VDDQ with DRAM VDDQ.
Default Gear mode for DDR5 is Gear 2 (Gear 1 will not work), with POR for 1 dimm per controller being 4800 mhz and 2 dimms per controller being 4000 mhz. The default base to clock ratio for DDR5 is 100:100, and unlike Rocket Lake, the 100:100 and 100:133 ratios seem to perform pretty well.

For the three gear modes (1/2/4), gear 2 requires that the dram ratio be divisible by 2, while gear 4 requires a divider of 4. So 4800 at 100:100 is fine. But 4900 is *NOT* since it’s not dividable by 2 or 4.
Gear 4 may only be worth using at 8000 mhz +.

DRAM Timings:

Use even numbers for TCL and TWCL, odd numbers don’t work.
TRP and TRCD can be individually adjusted. For questions about memory OC please ask cstkl1. I can’t help with memory OC.

Rough Description at Gear2:
Fmax VDD VDDQ TXVDDQ MC VDD SA Able to run CMD Rate 1T
2* Hynix SR 5800 1.3 1.25 1.25 1.25 1.25 yes
4* Hynix SR 5200 1.2 1.2 1.2 1.2 1.25 no
2* Hynix DR 5400 1.3 1.25 1.25 1.25 1.25 no
4* Hynix SR 4200 1.2 1.2 1.2 1.2 1.35 no
2* Micron SR 5600 1.35 1.4 1.4 1.34 1.2 no
4* Micron SR 5200 1.25 1.25 1.25 1.25 1.25 no
2* Micron DR 5400 1.25 1.25 1.25 1.25 1.2 no
4* Micron DR 4200 1.2 1.2 1.2 1.2 1.35 no
2* Samsung SR 5800 1.435 1.435 1.435 1.34 1.25 yes
4* Samsung SR 5200 1.35 1.35 1.35 1.25 1.25 no

You can definitely get 6000 and beyond, depending on lottery+ running with Hynix or Samsung but mem test stability depends on the IC quality. Watch your memory cooling at higher volts!

 

Next section: CPU Core OC

[Falkentyne]

Now on to the cores and overclocking methods!

CPU CORES, Overclocking, Voltages, etc.

 

First, people need to understand the traditional method of overclocking.
Always in the past, you started with usually some sort of "base clock" or PCI frequency clock and CPU multiplier. Often set with onboard jumpers (or even changing clock crystals before that). Eventually the PCI frequencies started becoming locked to the base "FSB", but you still had multipliers. Then eventually we started having a "base clock" only (BCLK), which you could use in certain overclocking or XOC scenarios (increasing this would also increase the memory frequency so care was needed),

 

But the same old school treatment was still used in the end--you set a target CPU frequency, target voltage, and loadline calibration, test for stability and save your profile and off you go. With newer and faster multi-core processors with increasing core counts, experienced overclockers started noticing that, when stress testing with useful tools that could actually show calculations on precise physical cores directly, they would see that their unstable overclocks would *always* fail on one or two SPECIFIC CPU cores all the time.

 

Prime95 was the best program for testing this, especially since it started getting updated for modern processors (30.7 beta 7 is Alder Lake compatible, but changes to FFT and thread sizing still needs to be done for this new platform). So whenever you tried to go for your high overclocks, you would always be limited by the WORST CPU cores, even though all the cores were calibrated to run at close to the same overall VID (so the quality wouldn't vary as much as a SP104 chip vs an SP50 chip, for the V/F point frequencies below 4800MHz. You can find some difference from 4800MHz to 5300MHz, for example!)

 

First a few words.
1) Disabling all E-cores will give you higher maximum clocks (usually at least +1 bin) on the P-cores. P cores also have access to the full L3 cache if E cores are disabled.
2) Also, disabling all E-cores allows you to yeet the ring ratio. Ring can go up to x50 if E-cores are disabled. With E-cores enabled, you are not going to get much higher than x42 to x44.
3) There is some strange relationship between the ring (cache) and the E-cores. If you overclock the cache too high with the E-cores enabled (e.g. 44+), you may encounter BSOD’s that look identical to “memory instability” errors (e.g. “Memory Management, IRQL_NOT_LESS_OR_EQUAL”. This is beyond me. CSTKL1 is the one to refer to with these.
4) There is also some sort of relationship between the E-cores and memory overclocking as well when pushing high memory clocks possibly with respect to the Atom L2 cluster 0 and cluster 1 voltages.
5) For every E core that is enabled, you seem to need about ~7mv more voltage for stability. So all 8 e-cores enabled seem to need about 56mv (0.056v) higher vcore. Might be the E-cores are siphoning power from the P-core supply.
6) For every small core enabled, you lose about an estimated ~15.85 MHz in P-core fully loaded frequency. So for all E-cores enabled (vs them all disabled), expect about -120 MHz off your max fully loaded clocks compared to all E-cores disabled.
7) VMAXSTRESS seems to not be supported on this platform. You can use VR Voltage Limit (mv) to limit your target load voltage (before vdroop) when using adaptive voltage modes.
8) Thermal limits may be hit around 1.3v die sense voltage and >210 amps of current. Maximus boards can monitor CPU Current (Amps) in EC in HWinfo64 (newest version) or on OLED (Maximus Extreme).
9) There are THREE SP ratings. One for P-cores, one for E-cores and the global SP. You can see them in Asus AI settings. I am uncertain how the global SP rating is affected by this.

 

For a typical CPU, 5.1 GHz on P-cores seems to need about 1.17v (or more) VMIN for heavy stress full load, and for very light loads, 5.4 GHz @ 1.30v. Average ballpark for all core OC may be 5.2 ghz and for P-core only, 5.3 ghz. You may run into thermal limits with P-cores at 5.3 ghz at full load.

For the small cores, maybe except 3.9 GHz @ 1.05v for full thread heavy workloads and 4.3 GHz @ 1.25v for very light loads.

 

Some rails overview: (POWER RAILS)

 

CPU Input Voltage (VCCIN AUX), external default value 1.8v rail, feeds the FIVR. Don’t care about this unless LN2.
CPU 1.8v small rail, external, default value 1.8v, may feed PHY/PCIE, don’t bother.
CPU Vcore. FIVR rail type, uses SVID for default, feeds big+little, important to care about.
CPU GFX, external SVID, feeds GT, care about if you’re using the iGPU.
CPU VCCSA system agent, SA VID for “set”, IVR VCCSA for “get”, FIVR rail type, default value based on SVID, care about it for memory OC.
Memory Controller voltage, IMC VDD, external 1.1v rail, feeds another part of mem controller, care about it for memory OC.
IVR Transmitter VDDQ, VDDQ TX Voltage for “Set”, IVR TXVDDQ for get, FIVR rail, 1.1v default value, voltage level for the transmitter part. Important for memory OC
PLL Termination Voltage (VTT), external 1.05v default rail, Sustain and “Sustain gated” rail, only care about this for LN2 OC.
CPU Standby Voltage, external 1.05v rail, sustain/gated, only care for LN2 OC.
IVR VCCIO Analog: ignore this.
IVR Atom L2 Cluster 0, Atom L2 cache cluster 0, need for LN2, effect is undermined for regular OC, may or may not affect Cache OC with E cores enabled, or MEM OC. Cstkl1 knows more about this.
IVR Atom L2 Cluster 1: same
PCH: 1.05v external rail, primary core voltage, no need to care about this
PCH 0.82v rail: primary “Well(?)” voltage, ignore this.

 

“Current Excursion Protection” is similar to VIN Tracker on X299, enabling it causes “Phantom Throttling” (I do not know anything about this).

 

There is some kind of bug where the CPU PLL, when cold, can keep upping frequency limitlessly, as if the PLL gets locked on a certain Freq but reports a value it’s not really using. People have been exploiting this for false validations. To avoid this there is a setting in Tweaker’s Paradise: FLL Mode. Set FLL OC Mode to Normal to avoid this bug.

 

Just like RKL, ADL’s big cores have their own individual PLL so each one can run different ratios at the same time. The Atom cores however come In a cluster of 4 and they not only share the same PLL but also the same DTS sensor, so a pack of 4 can only run the same ratio and they read the same temp.

 

OC based on some testing of samples:

 

P-core Frequency max: 5400 mhz, 1.30v die sense voltage LIGHT load, 5100 mhz @ 1.17v die sense HEAVY load.
E-core Freq max: 4300 mhz, 1.25v die sense LIGHT load, 3900 mhz @ 1.05v die sense HEAVY load.
V-latch is on Apex and Extreme, just like on Z590.

 

I have found the best heavy stress test for ADL is “Stockfish” Chess engine. You can install it in “Arena” UCI client here.
https://stockfishchess.org/
http://www.playwitharena.de/
You need to load the exe into the client in the “Engine” section, make sure you configure the # of threads or it will only run 1 thread by default!! This is a very heavy high stress test. I have found passing “stockfish” on all threads (16 for P-cores only, 24 for P+E) requires about 50mv-60mv MORE VOLTAGE than you need to pass Cinebench R23 for 30 minute loops. If you can pass stockfish, you’re FULLY AVX stable!

BMI2 instruction set (may be heavier than AVX2, not sure)
https://abrok.eu/stockfish/

Prime95 30.7 beta 7 is required for ADL support. This with small FFT may be even harder to pass than stockfish. Large FFT + AVX disabled is very good for RAM OC testing. Try it.
https://www.mersenneforum.org/showthread.php?t=27180

 

Intel Turbo Boost 3.0 and their TVB would allow both an extra clock bin if chips ran below a certain temp, and "favored cores", which would allow the best cores to run at one or two thread workloads at the highest boost clocks, which would be linked to those cores (e.g. 5.3 GHz on up to two cores).

As far as trying to override this behavior with "all cores", So you could have for example, some good cores that were capable of running at 5.5 GHz at 1.4v load, if kept under 70C, while the worst cores could only handle 5.2 GHz at 1.4v load, but up to 90C. But without going cold, you wouldn't be able to run all eight (or ten, or however many you had) cores at 5.5 ghz at full load, for instance.

 

In Rocket Lake, as mentioned in this guide: https://rog.asus.com/forum/showthrea...s-have-Changed , I mentioned that each core has its own PLL, which means that different cores can run at different frequencies. This, along with massive stability improvements, which was overlooked by every tech reviewer (how many reviewers even mentioned the Parity issue on Comet lake? Did any of them play Minecraft?)

 

Combined with "OC TVB", which allows extra binning steps beyond what Intel specified--based on a temp target (below minimum floor temp, between floor to ceiling, and beyond ceiling), you could help control how the cores boosted in clocks in core specific workloads.

Also the V/F curve chart allowed you to change the actual "VID" target of the CPU at different 'steps', by setting an offset for the VID (in fractions of a volt).

On this new platform, VccIA is the voltage rail shared by P-cores, E-cores, and Ring. Each P-core, each E-core cluster, and ring have their own V/F curve (so 8+2+1=11 in total).
Voltage of VccIA is the highest of those 11. Highest voltage wins is the rule you need to follow.

(thank you to skatterbencher for the clarification).

 

New to the Asus Maximus Z690 boards is an overclocking feature, specific core adaptive voltage. This is an extension of adaptive voltage, which itself uses CPU VID, combined with AC/DC Loadlines for full load behavior.

 

There is still only 1 VccIA rail shared by all P-core, E-core, and Ring. So, there is no independent voltage. Therefore, Per Core Specific Adaptive Voltage allows us to set an Adaptive Voltage for each core. As you know the Adaptive Voltage is mapped against the “OC Ratio”. The OC Ratio is the highest configured ratio among all your settings. Normally there is 1 global adaptive volt for the OC ratio and all cores will use that V/F for interpolation. Even if they’d be able to run that ratio at lower volt. Per Core Specific Adaptive Voltage changes that to different adaptive voltage per core mapped to OC Ratio So for example, let’s say you have 4c that can do 55X. 1st core at 1.325V, 2nd at 1.35V, 3rd at 1.375v, and 4th at 1.40v.

Before this feature, if you run 1C, 2C, 3C, 4C load at 55X, it would always set 1.40V.
Now, if you run core 1 + core 2 at 55X and other cores are sleeping, it will run MAX(1.325,1.35)=1.35V.
That’s because it takes the specific core adaptive volt into account, not the global one.

(Thanks to skatterbencher for this information).

 

Important for setting V/F offset points :

 

Roberto has a method of dealing with the “missing” frequency points (set by Pcode) from 4.9 to 5.2 ghz. His method is based on using LLC1.
it's a good practice to keep vf#11 + offset = adaptive voltage.... Example If vf#11 = 1350, If you set an adaptive voltage of 1.460 You shall apply a vf#11 offset = (1460 -1350) = 110mv.

 

I MUST emphasize that this is specific to robertosampiao’s type of setting of LLC1. if a typical overclocker decides to use a scenario of LLC4 ~6 , setting 1460 + vf11 +110mv you are doing a volt of 1570.

 

ADL has 11 VF Points

• 1-7 are unique points, 11 is OC point (user can change this ratio). These are the only ratios user can change on this curve.

• 8-10 are copies of 7 (seem to be placeholders from Pcode, maybe for a future product?)

• 7 is the last unique default point

• The rule appears to be when ratios are the same, point 7 must be >= point 8 otherwise it will MCA. MCA is “machine check” BSOD. It means Game Over. Please try again. So PLEASE IGNORE POINTS 8 through 10 !!!

• Pcode does not like it at all when point 7 voltage offset is less than point 8

• If you want to program 7 negative, you must program point 8 negative first

• If you want to program point 8 positive, you must program point 7 positive first

• If you don't follow this rule then Pcode throws MACHINE CHECK ERROR.

• If programming a negative offset to point 7, best way is to start with point 10 and program it negative, then go to 9,8, and 7 programing them all the same negative value

• If programming a positive offset to only point 8, best way is to start with 7 and then go to 8,9, and 10 programming them all to the same positive value

Thank you to Shamino @ Asus ROG team for helping to clarify this.

 

Allow me to quote another Intel engineer who helped me with this difficult step:
“ Remember HIGHEST VOLTAGE WINS.”

Also please remember: if global adaptive voltage< vf#11, adaptive will be ignored.
Please remember this rule! And this works with OCTVB, along with specific core usage, which is explained in great detail in Skatterbencher's videos here.

https://www.youtube.com/watch?v=FWPTJDrping
https://www.youtube.com/watch?v=BIV--SXjsHU
https://www.youtube.com/watch?v=fBrlgLZrFaI (current platform)

So for example, you can have something like this (this is based on P core settings):
x57 on 2 cores active, running at a high voltage as a high clock would need a higher VID.
x55 on 4 cores active, running at a slightly lower voltage (VID)
x53 on 6 cores active, running at even lower.
x51 on 8 cores active, running at your standard voltage you previously tested as needed for stability.

So now for your single threaded workloads or games that only use a few threads, you can boost them to higher clocks without having all the cores having to run at higher voltages!

You can also combine this with the Specific Core Ratio Limit to specify which exact physical cores you want to run at these boost clocks, as well as use Asus preset profiles for OCTVB for a higher total boost bin (or you can create your own specific core ratio limit).

Before you start with Specific core and adaptive specific core, you must first find out what the "VMIN" stable is for all core overclocking (just like you're used to). You will need this as this will influence what you will set for the Global Adaptive Voltage setting (which will be the ceiling and used for all core workloads).

[Falkentyne]

More on Specific core OC, Loadlines, Suspension and formulas.

 

Voltage Suspension

A new feature, this is designed to keep the voltage in a custom range, based on temps. This was the hardest feature to understand, so I’ll use Shamino’s explanation. Cstkl1 was able to use this feature for benching at high frequency.

 

A more technical term would be V-Clamp:

If v<x: V=x;
If v>y:
V=y;

 

It tries to achieve this with a hardware circuitry, mimicking a dual regulator scenario. Best way to picture it would be that one regulator would always be obeying exactly what the CPU VID wants, while the other is trying to correct it to what you want.

Mainly useful for VID mode, usually to modify PBO’s V/F behavior.

 

The Voltage Ceiling’s auto is 1.55v. You can decrease it for undervolting in SVID adaptive mode.

Efficacy of up to 0.3v, meaning if voltage before V-Clamp is 1.5v and ceiling is 1.3v, then result will be 1.3v. If voltage before V-Clamp is 1.5v and ceiling is 1.1v, then result will be (1.5-0.3)=1.2v.

The Voltage Floor’s auto is 0v, meaning absolute ground floor. You can increase it for scenarios where idle low power state voltage is insufficient.
Efficacy of up to 0.3v, meaning if voltage before V-Clamp is 0.2v and Floor is 0.4v, then result will be 0.4v. If voltage before V-Clamp is 0.2v and Floor is 0.7v, then result will be (0.2+0.3)=0.5v.

 

There are two modes: static and dynamic. In Dynamic you can make your own Volts/Temp curve.
The point is in dynamic VF, you run higher freq with lower temp but with higher V. This gives you finer control of V with regards to T.
You can use both ceiling and floor dynamically, and you could have floor_low_vmin lower than ceiling_low_vmax as a safety net and floor_hot_temp to be slightly higher than ceiling_hot_temp.

 

Then have the floor_high_vmin lower than ceiling_high_vmax as a safety net and floor_cold_temp to be slightly colder than ceiling_cold_temp.
This gives it a nice narrow road for the VT curve to travel on.

After setting this, the ceiling and floor will be dynamically shifting according to cpu temp. Obviously if ceiling and floor mirrors each other than you try to force an exact linear VT curve.

After setting this, the ceiling and floor will be dynamically shifting according to cpu temp. Obviously if ceiling and floor mirrors each other than you try to force an exact linear VT curve.

 

I understand that many people may get confused about this feature and may need a graphical representation of it. I suggest Skatterbencher’s splendid video of this, done on the Crosshair AMD board. The concepts still apply here.

https://www.youtube.com/watch?v=pabeE8cCv4k
Also explained in his new published guide for ADL. This may be easier for people to follow visually.

 

 

More on OCTVB, Adaptive and Specific Core and loadlines.

 

RobertoSampiao has found some combinations of loadlines that provide good voltages and temps results . In his tests, settings work BEST with low level Loadline Calibration (Level 1 -1.7 mOhms) and a little aggressive AC Loadline (set manually to 0.6 mOhms). DC Loadline should be set to the same mOhms as loadline calibration (1.7 mOhms) so the VID value doesn't sway too far from the "Active" Vcore value the active cores are using. This was a way he found to manage voltage at full load and take advantage of Vdroop to hit high core frequencies.

I still do not fully understand the specifics, but I believe part of this limitation is from Intel NOT having any V/F points between 4800 MHz and 5300 MHz, which are instead set by “Pcode” or interpolation. This is a huge jump in default VID between these points, so to "cushion" this behavior, we need to use a VERY droopy LLC so your CPU's won't get overvolted at full load.

RobertSampiao is working on an XLS excel document to help end users with determining their optimal V/F voltage offsets for specific core overclocking and their adaptive voltages, based on their V/F table as well as the ACLL and load targets they are aiming for.Ok, so now that’s out of the way, let’s get into the details.

 

This information is purely RobertSampiao’s hard work. He spent many many hours doing all of this. I admit I was very overwhelmed with many of these changes, but with his new specific core, adaptive voltage guide, I was amazingly able to get my two favorite cores running at 5.6 ghz, which gave me a higher than 900 CPU_Z singlethread score! If you need that extra boost in performance, he’s the one who will help guide you to this.So, first:

 

OCTVB:

The TVB overclock consists of changing boost pulse patterns to achieve higher frequencies than standard frequencies when there is a thermal opportunity.

 

This is the I9-12900K (ES) Stock core configuration:

P: 52x1 – 51x2 – 50x4 – 49x8
E: 39x4 – 37x8
Full load: P-49x/E-37x

 

E.g. You can change the Boost of the 12900k to work this way:
P: 57x3 – 55x5 – 53x8
E: 42x4 – 41x6 – 40x8
Full load: P-51x/E-40x

 

What we do, in a simplified way, is to configure the TVB so that if the workload is low, the frequency is high, and that when the workload is high, the frequency goes lower.
By changing the TVB, or rather by overclocking on TVB, we get to Asus OCTVB.

 

Important:
For OCTVB to work, you need to enable C-States!

 

“Adaptive Voltage” e “VF curve”:
Unlike the "fixed Voltage", the "Adaptive Voltage" and "VF curve" behaves as to monitor the frequency. Higher frequencies require higher voltages, lower frequencies, lower voltages.

Every processor comes standard with an internal VF curve that we can't change. Asus MBs allow us to add an offset (positive or negative) to these points of the original curve. So, we can say that Asus allows us to change the CPU Voltage x frequency curve.
This chart is in the Asus BIOS under V/F settings. There is also more information under AI settings and the “CPU Configuration” menu as well, over on the next bios page.

Asus allows us to change the voltages of all points through the offset and allows us to change the frequency only of the last point through the "By Core" setting.

So for our TBV overclock, the important points will always be the last two. The points VF#7 and VF#8 for the 10900K and 11900K and the POINTS VF#7 and VF#11 for the 12900K(ES).

 

Points VF#8,9 and 10 will not be used and must remain in AUTO.

 

LLC, AC_LL & DC_LL:
The first step in planning overclocking is to set the full load frequency. But for everything to work well, and as expected, we must first of all set up the LLC, AC_LL and DC_LL. If the chosen Full Load frequency has a unique VF point for this frequency, we will be more free to choose LLC, DC_LL and AC_LL.
Otherwise, if the Full Load frequency does not have a unique VF point, we will have to choose the best Load Line set that allows us, through interpolation of the points, to set the voltage referring to the frequency chosen for Full Load. The basic rule of adaptive voltage and TVB overclock (OCTVB) is to work with vdroop to your advantage. This way using a less aggressive LLCs will give you greater leeway for high frequencies. In a simplified way, load line should influence overclocking as follows:

 

Low loads, low Vdroop, high voltages, high frequencies.
High loads, high Vdroop, low voltages, low frequencies.
You can configure the TVB overclock using any LLC, it all depends on your processor and what you want to do with it.
Maximus Z-690 Extreme LLC Impedance:

I believe the LLC levels are similar to the LLC levels on Rocket Lake, which I listed in The Rules have Changed guide.
LLC1: 1.7 milliohms
LLC2: 1.46 milliohms
LLC3: 1.1 milliohms
LLC4: 0.98 milliohms
LLC5: 0.73 milliohms
LLC6: 0.49 milliohms
LLC7: 0.24 milliohms
LLC8: 0.01 milliohms (flat).

 

Note that LLC8 should NEVER be used except for testing purposes, and ONLY on fixed vcore and preferably ONLY at LESS than 1.25v
The DC Loadline Problem AND WHY TOO MANY TECH TUBERS THINK THE ROCKET LAKE AND ALDER LAKE
CPU’S USE 250-350W AT STOCK.

The impedance values of the DC_LL must be used according to the LLC chosen, so that the CPU performs its internal voltage and power calculations accurately.

Impedance stake:
DC_LL=LLC: The CPU makes correct VID and power calculations;
DC_LL<LLC: The CPU performs higher-than-real VID and power calculations;
DC_LL>LLC: The CPU does lower than real VID and power calculations.
So, the rule number 1 is ALWAYS TUNE The DC_LL according to the LLC chosen.
When using FIXED Vcore, the vcore you set is almost never going to match the CPU VID’s own target
So already, the CPU Package Power is going to vary from VRM power (what the CPU is really using).
Then if DC Loadline is set so that CPU VID @ Load is drastically different than CPU Vcore at load, Package Power can end up reporting as much as 100 watts HIGHER than what the CPU is really using.

Below are some loadlines suggestions for the 12900K”

LLC#1
DC_LL = 1.7
AC_LL = 0.60

 

LLC#2
DC_LL = 1.46
AC_LL = 0.50

 

LLC#3
DC_LL 1.1
AC_LL 0.35

 

LLC#4
DC_LL 0.98
AC_LL 0.30

 

These are the values that we will be recommending for end users when using the “Adaptive Voltage” or specific core adaptive voltage settings.

 

Setting the Full Load frequency:

 

51x is a Full Load frequency that almost all processors can support, even with an AIO type cooling solution, so we'll follow this example.
Now we must find out what the minimum voltage for the full load frequency, optimizing the working temperature of the CPU and the dissipated power.
To find the minimum voltage for Full Load we need to synchronize all cores in 51x.

 

The traditional way would be to use "Sync All Cores" in 51x and "fixed Voltage", but we will do something different to start using "By Specific Core".

However I strongly recommend that end users determine FIRST, what their true VMIN (minimum load voltage required for stability) at x51 sync all cores (remembering only the P-cores can run at these speeds). Start with LLC4, stress test in the applications you daily (e.g. games or your rendering).

You may want to have an extra profile for power virus heavy AVX programs like “Stockfish” chess engine, which I use for my own hellish worst case testing, or if you really need room heating during the winter, Prime95 30.7 build 7 (REQUIRED FOR ALDER LAKE SUPPORT), AVX2, AVX1 or SSE2. AVX512 will work if you disable the E-cores but you may want to increase CPU Current Capacity (this may be part of the reason why AVX512 isn’t “officially” supported—I had the entire VRM’s instantly shut off trying to do AVX 512 @ 5.2 ghz the instant I pressed “start”. CPU current capacity prevented that, and I was only pulling 210 amps and was at 105C in one second (my throttle point).

Anyway enough rambling. Find your true VMIN at LLC4. Then you can test LLC3, LLC2 or LLC1 and see if your VMIN changes (lower vcore needed) due to better transients (you can check with the Asus Volticon if you have the Apex or Extreme, or reset (while at full load, use the dip switches) and look at the values for “VLATCH-MINIMUM” on the OLED or HWInfo “Asus EC” section).

Ok now that you found your x51 all core fixed VMIN it’s time to start tuning.

 

Defining Load Lines:

Now we must choose which LLC we will use.

Let's start by testing LLC#1: (Roberto’s suggestion)
Now let's tune AC_LL and DC_LL to LLC#1

LLC#1
DC_LL = 1.7
AC_LL = 0.60

 

I must emphasize: this method of AC<DCLL setting is just trying to manipulate inputs to get the outcome desired -> lesser V. from a technical point of view it is illogical because AC LL will always be>= DC LL in reality.

IA VR Voltage Limit
Asus included in the BIOS of its Z-690 MBs the control "IA VR Voltage Limit".
This control limits the VCCore voltage to the selected value, preventing the CPU from reaching frequencies that require higher voltages than the selected one. In practice this control limits the maximum CPU frequency based on the voltage.
The default value (AUTO) is 7999mv, that is, by default there is no frequency limitation due to Vcore voltage. This control will be very useful for limiting the highest frequencies while maintaining system stability. As a suggestion the value of 1500mv is quite reasonable. This value is applied BEFORE VDROOP, so the final voltage your CPU will need will be lower than this. Focus on diesense voltage for accurate readings. Note that this setting is ignored (afaik) when using fixed manual vcore.

 

*Edit by Falkentyne*

In my own tests, I found that a VR Voltage Limit of 1520mv (1.52v)—remember in BIOS you must enter this in millivolts--prevented the 2 best cores from boosting to their 5.6-5.8 ghz single thread limits on specific core adaptive voltage that I was testing. I determined this was due to “AC Loadline” requesting a VID higher than 1.50v, BEFORE DC Loadline got ahold of it for reporting to the OS. By slowly increasing VR Voltage Limit, I was able to maintain a higher boost on the two best cores, topping out at 5.6 ghz at a VR Voltage Limit of 1650mv. So in our specific core adaptive OC settings, slowly raise this if you find yourself clock throttling (without high temps). If you are nervous about setting high volts while working with adaptive or specific core adaptive voltage, please set this value to 1520mv. Then as you get more comfortable and understand how your processor works, you can increase this. If LN2 mode is NOT enabled, the maximum value that will be used is 1720mv.

 

System startup:

Start the system with the following settings:

LLC=#1
AC_LL=0.60
DC_LL=1.70
IA VR Voltage Limit = 1500
Voltage Optimization = Enable
By core = 51x8

 

It's time to test system stability in Full Load.
Run the CB-R23 and check the stability of the system.
If system is stable, use VF#6 to reduce the 51x full load voltage to the minimum full load voltage you found before.
If the system is not stable use the LLC#2:

 

LLC=#2
AC_LL=0.50
DC_LL=1. 46
IA VR Voltage Limit = 1500
Voltage Optimization = Enable
By core = 51x8

 

Keep increasing load line settings until you get stability by running the CB-R23.
Note: It is very likely that using the LLC#1 settings the system will be stable, with good voltages and temperatures. With the system is stable, knowing the minimum voltage for 51x, you can offset VF#6 the reduce the 48x voltage and in this way reduce de 51x (by interpolation from 48x to 53x).
You can use VF#7 too, but be care with stability of the 53x and above.
Roberto's tests suggest that the configuration below will be stable using average rating SP CPU’s.

 

LoadLines:

LLC=#1
AC_LL=0.60
DC_LL=1.70

By Core:
P: 54x3 – 53x5 – 51x8
E: 41x4 – 40x8
OCTVB:
+2Boost Profile
Voltage Optimization = Enable

Voltage:
Adaptive Voltage=1.460
IA VR Voltage Limit=1500
VF#11 offset = 1.460 – Native VF# 11 voltage.

*** If needed, use VF# 6 to tune the 51x full load voltage ***

Your system will run like this:
P: 56x3 – 55x5 – 53x8
E: 41x4 – 40x8
Full load: P-51x/E-40x

If you are stable with these setting, you can try to lowering Adaptive voltage below 1.460 or try to increasing pre-boost frequency to:
P: 55x3 – 53x5 – 51x8.

It is also possible to increase the IA VR Volt limit to 1600mv—up to 1720mv.

 

“ROG True Voltician”. –the coolest ROG toy ever. The Apex and Extreme will come with this. It is your own personal oscilloscope. Software is included or available on ROG utilities website section. One point must be hooked up to ground (be careful if using a fan pin for ground, make 100% sure you put the jumper on the correct pin). Other points are onboard. You can use the host system or use a USB cable and use a second computer to read Voltican graphing output.

[Somerandomtechyboi]

Damn thats alotta potentially useful info for any overclocker (if any even exist anymore that is considering cpu oc has been dead for a long time), since ddr5 has the voltage regulator on the stick itself, is there any way to voltmod them if they are the ones that only go to 1.4v?

 

20 minutes ago, Falkentyne said:

I encountered OCP with AVX512 at 5.2 ghz

Is ocp something you can disable in the bios? Maximus is supposed to be a high end extreme overclocking board and its crippled by damn ocp ;-;

 

Reminds me about my p5q, why the hell even have a 2.1v max setting on vcore when setting over 1.8v will cause it to shut off? prob among the worse board crowd on 775 with msi cause low fsb capability

[Mister Woof]

Lots of good information. It's unfortunate so few will care because of their biases.

[Somerandomtechyboi]

1 minute ago, Mister Woof said:

Lots of good information. It's unfortunate so few will care because of their biases.

Yea cpu oc is dead so no wonder, though the ram oc info is gonna be very useful for most ppl since ram oc is literally the only thing that still yeilds a performance increase without turning your pc into a room heater, not to mention if you got an igpu then obv youd oc the rams

[Camofelix]

Super happy to see the AVX 512 options being included! That and the increase in downstream bandwidth for accelerator cards (GPU's, TPU's, intel PHI etc.) should make this a great little simulation machine!

 

Something I'm still looking to see is how disabling the e-cores effects the L3 access for the P core's.

 

The above also means that, for AVX interested people, the 12900k is (mostly) irrelevant, and the 12700k looks like one heck of a deal.

 

edit: Worth mentioning that by disabling the e-cores, we also get rid of a lot of the complexity around thread scheduling

Edited November 4, 2021 by Camofelix
added mention of not having to deal with new scheduler

[Falkentyne]

5 hours ago, Somerandomtechyboi said:

Damn thats alotta potentially useful info for any overclocker (if any even exist anymore that is considering cpu oc has been dead for a long time), since ddr5 has the voltage regulator on the stick itself, is there any way to voltmod them if they are the ones that only go to 1.4v?

 

Is ocp something you can disable in the bios? Maximus is supposed to be a high end extreme overclocking board and its crippled by damn ocp ;-;

 

Reminds me about my p5q, why the hell even have a 2.1v max setting on vcore when setting over 1.8v will cause it to shut off? prob among the worse board crowd on 775 with msi cause low fsb capability

Still seems to be confusion (within Intel, no less) as to whether we were supposed to get AVX 512 in the first place.

Yes, CPU Current Capacity -->140% (instead of auto) avoids the OCP.  I reached 105C in 2 seconds anyway so it was pointless, I was thermally limited at 5.2 ghz small FFT AVX512.= > 1.3v die sense load vcore, amps was 210A, uncoolable on 360mm AIO.

[freeagent]

Awesome stuff buddy! Thanks for taking the time to put this all down

 

Because inquiring minds did want to know!

 

I might have to get one, because I do have an AMD right now, but I like both manufacturers. I was with AMD first until I got burned, than was with Intel the longest.. 10+ years. Only got the AMD because they were giving Intel such a good spank I had to get in on it lol 

 

Edit:

 

The CPU I want is what comes after ADL

[Camofelix]

4 hours ago, Falkentyne said:

Still seems to be confusion (within Intel, no less) as to whether we were supposed to get AVX 512 in the first place.

Yes, CPU Current Capacity -->140% (instead of auto) avoids the OCP.  I reached 105C in 2 seconds anyway so it was pointless, I was thermally limited at 5.2 ghz small FFT AVX512.= > 1.3v die sense load vcore, amps was 210A, uncoolable on 360mm AIO.

Seems like the Peizo cooler from last gen might help? that or proper high flowrate water cooling.

 

Still following up with some guys on AVX-512 implementation- seems this is actually the sapphire rapids version, so we might be able to get even more performance out of this chip, even at current frequencies with a simple recompile with the latest version of ICC/LLVM. 

[Wolverine2349]

Are Samsung DDR5 chips still best as with DDR4 RAM?

 

Or is Hynix better.

 

Can Samsung run at 1T command rate like Hynix?

[DarkSmith2]

1 hour ago, Wolverine2349 said:

Can Samsung run at 1T command rate like Hynix?

there is no 1T command rate with Alderlake, its 1N fake bullshit.

[Falkentyne]

On 12/29/2021 at 8:13 AM, DarkSmith2 said:

there is no 1T command rate with Alderlake, its 1N fake bullshit.

Before making a comment like this, I think you should clearly explain the difference between 1T, 1N and N=1.  Because 90% of people who read your message will have no idea what you're talking about.  

 

And yes there is 1T on Alder Lake.  AIDA64 tests won't pick it up with DDR5 (unlike DDR4).  But game tests will show serious improvements especially with 1% lows.  I don't know about DDR4.  And there is no "Gear 1" with DDR5 because a section of the cycles are in one pass (unlike Gear 2 with DDR4).

 

Please don't ask me for questions about this as I don't know and I won't answer, but somewhere around 46 minutes here is a full explanation by Skatterbencher.