Threadripper coming: split for low and high end, 8 channel memory

[The King of the Undead]

1 hour ago, Den-Fi said:

My body is ready.

it is PGA.

[Guest]

2 minutes ago, will4623 said:

it is PGA.

No, this is Patrick.

[Fasauceome]

4 minutes ago, will4623 said:

it is PGA.

PGA threadripper be like

[The King of the Undead]

3 minutes ago, Fasauceome said:

PGA threadripper be like

*snores*

[Taf the Ghost]

1 hour ago, S w a t s o n said:

As excited as I am for the 16 core 4 channel TR, where the fuck is the 3950x??? It's September Lisa, the clock is ticking...

It's it supposed to be Sept 23rd?

 

Edit: looks like it's just Twitter rumor mill not official yet.

[leadeater]

8 hours ago, porina said:

Anyone dare speculate on timing?

01/04/2020 (proper date/time format)

[TechyBen]

On 9/9/2019 at 3:01 AM, BiG StroOnZ said:

Wondering if the split has anything to do with this (for AMD to be even more competitive):

 

Arguments aside. If Intel double their price-performance metric in a single half generation, I will fall off my chair.

[TechyBen]

On 9/9/2019 at 5:43 AM, VegetableStu said:

one last thing before i leave this thread temporarily for my own good: i set aside a thread to anticipate any TR announcement event, and in it i had a list of current CCD counts in EPYC 7002 parts.

 

the higher the CCD count the more Lx cache it has:

• 8c (you read that right)
  • 1x8c 7232P (you read that right)
  • 2x4c 7252
  • 4x2c 7262 (you read THAT right)
• 12c - 2x6c 7272
• 16c
  • 4x4c - 7320P etc
  • 2x8c - 7282
• 24c - 4x6c - 7420P etc
• 32c - 4x8c - 7502P etc
• 48c - 6x8c - 7642 etc (oddly does not have a single-CPU part)
• 64c - 8x8c - 7702P, etc

 

oddly there wasn't a 6x6c, but I think it might be a viable alternative, like for example 4x8c on sTRX4 and 6x6c on sWRX8

I'm interested in how a home PC (gaming etc) performs with 128mb cache... my first PC had that in RAM!!! 

[porina]

4 minutes ago, TechyBen said:

Arguments aside. If Intel double their price-performance metric in a single half generation, I will fall off my chair.

It can be achieved in a combination of two ways: increase performance, lower selling price. The only question is what balance of those factors are used. AMD have historically chosen to price low compared to Intel (and nvidia). If the costs to produce are low, that helps enable that without impacting profits. Since pricing is a choice, personally I like to analyse the hardware independently of price to understand their inherent strengths/weaknesses, before factoring in value later on when buying.

 

2 minutes ago, TechyBen said:

I'm interested in how a home PC (gaming etc) performs with 128mb cache... my first PC had that in RAM!!! 

My first PC had a 250MB HD! Never mind ram... As often the case, it will depend on the application. Ryzen architecture is essentially in chunks of CCX. If it isn't stored on local CCX, it has to go back to ram. This is different from Intel where all L3 cache is available to any core. Some tasks that benefit more from a unified L3 may still favour Intel, but code that is more easily split will scale with the brute force of throwing cores at it.

[leadeater]

8 minutes ago, porina said:

My first PC had a 250MB HD!

You had an HDD!? Dual floppy only here 

[leadeater]

9 minutes ago, porina said:

If it isn't stored on local CCX, it has to go back to ram.

I thought between CCX on same CCD could be done? Otherwise back to IOD. Really not sure on that, Zen 2 arch info is very light but maybe a review on Zen/Zen+ between CCX might help. I'm not even sure it matters either since L3 cache in Zen is more a dumping ground for the CCX so cross access might be a thing at all, designed not to be.

[porina]

10 minutes ago, leadeater said:

You had an HDD!? Dual floppy only here 

Think we could deduce an age range for people based on 1st systems, although it could also be skewed by when in their life they got their first PC. I got my first PC after I got my 1st car.

 

Actually, my first "PC" could be even earlier, if you include software emulation. I had PC Ditto on Atari ST. I recall Landmark benchmark rated it around 18% the speed of an XT, which was 8088 at 4.77MHz. So... really not fast!

[porina]

9 minutes ago, leadeater said:

I thought between CCX on same CCD could be done? Otherwise back to IOD. Really not sure on that, Zen 2 arch info is very light but maybe a review on Zen/Zen+ between CCX might help. I'm not even sure it matters either since L3 cache in Zen is more a dumping ground for the CCX so cross access might be a thing at all, designed not to be.

On Zen 2, it was stated that all CCX to CCX communication has to go via IOD, even if they were located on the same CCD. Reason given was to allow more predictable latency.

 

Kinda related (click through for thread for context):

 

[leadeater]

5 minutes ago, porina said:

On Zen 2, it was stated that all CCX to CCX communication has to go via IOD, even if they were located on the same CCD. Reason given was to allow more predictable latency.

Hmm then that has changed from Zen/Zen+. Most of the stuff I could find talked about latency consistency to the system memory across the cores, but on his Zen 2 architecture analysis article it says this:

Quote

AMD manages its L3 by sharing a 16MB block per CCX, rather than enabling access to any L3 from any core.

 

I'm thinking since each CCD has a SDF/IF in it and it's actually possible to have that data path it'll come at some later point when there is better market adoption and more reason to optimize. I guess it's just removing a potential problem point.

[cj09beira]

19 hours ago, Taf the Ghost said:

It's it supposed to be Sept 23rd?

 

Edit: looks like it's just Twitter rumor mill not official yet.

i just read somewhere that talked about it being on 30th

 

[porina]

1 hour ago, leadeater said:

Hmm then that has changed from Zen/Zen+. Most of the stuff I could find talked about latency consistency to the system memory across the cores, but on his Zen 2 architecture analysis article it says this:

Was there a short cut in Zen(+)? I don't recall testing that particular detail at the time.

 

1 hour ago, leadeater said:

I'm thinking since each CCD has a SDF/IF in it and it's actually possible to have that data path it'll come at some later point when there is better market adoption and more reason to optimize. I guess it's just removing a potential problem point.

I hadn't come across SDF as an acronym before, I have to thank google for the following when I searched for it... back on topic, it has never been clear to me how cores/CCX, IF, L3 are logically connected. CCX as smallest logical unit makes sense for scaling with what they have, even if I'd still prefer CCD to be such. The first processor beyond 4 core CCX will be interesting, and IMO a necessity as some point if they want to keep scaling up to ever higher core counts.

 

[leadeater]

30 minutes ago, porina said:

I hadn't come across SDF as an acronym before, I have to thank google for the following when I searched for it... back on topic, it has never been clear to me how cores/CCX, IF, L3 are logically connected. CCX as smallest logical unit makes sense for scaling with what they have, even if I'd still prefer CCD to be such. The first processor beyond 4 core CCX will be interesting, and IMO a necessity as some point if they want to keep scaling up to ever higher core counts.

IF is just the slightly broader term for things inside of it like the SDF. In Zen/Zen+ this was used for cores to access the other L3 slices, across CCXs. This gave slightly odd results in Ryzen, overall not that serious but with TR and EPYC these multiple different latency hops and accesses was a lot of trouble. In CCX, across CCX, cross die to CCX, across die to IMC. All levels of optimization hell lol.

 

Quote

AMD organized Zen in groups of cores called a CPU Complex (CCX). Each CCX consists of four cores connected to an L3 cache. The L3 cache is an 8 MiB 16-way set associative victim cache and is mostly exclusive of the L2. The L3 cache is made of four slices (providing 2 MiB L3 slice/core) organized by low-order address interleaved. Every core can access every L3 cache slice with the same average latency. When a certain core starts working on a chunk of memory it will fill up the L2 and as it continue to execute and fetch new data any spillover will find its way in the L3.

https://en.wikichip.org/wiki/amd/microarchitectures/zen#Scalability

 

Wikichip is pretty awesome, but not much on there for Zen 2 yet.

[The_Prycer]

On 9/8/2019 at 10:02 PM, williamcll said:

What even is the reason to buy low-end EPYC at this point then?

Threadripper is designed-as its name implies-to destroy tasks like video editing, machine learning, causing small blackouts in your neighborhood, and whatever other big tasks you set in front of it. It is not designed to be kept on all day though.

 

EPYC is the Enterprise version of Threadripper. Still a monster of a CPU, but with more stringent Quality Control standards and the consideration of being turned on and left on for 3+ years as well as being put in to rack mounted cases.

 

[Crowbar]

On 9/8/2019 at 11:40 PM, Fasauceome said:

On the other hand, maybe they'll manage an ITX TR4 motherboard, somehow

 

Maybe quantum superposition? The ram and CPU socket occupy the same region of space 

What cooler that's properly designed for threadripper is going to fit into an ITX form factor case?

[Fasauceome]

59 minutes ago, Crowbar said:

What cooler that's properly designed for threadripper is going to fit into an ITX form factor case?

We'll cross that bridge when we get to it

[RotoCoreOne]

Define low end...

[Drak3]

3 minutes ago, RotoCoreOne said:

Define low end...

In this context, the lower performance parts within the product stack.

[Jito463]

On 9/9/2019 at 9:22 AM, Den-Fi said:

My body is ready.

But is your wallet ready?

5 hours ago, TechyBen said:

I'm interested in how a home PC (gaming etc) performs with 128mb cache... my first PC had that in RAM!!! 

5 hours ago, porina said:

My first PC had a 250MB HD! Never mind ram.

5 hours ago, leadeater said:

You had an HDD!? Dual floppy only here 

1MB RAM, no HDD and dual floppies in a Commodore Amiga 2000, with an additional 5.25" floppy drive hooked up to a PC emulator (which I never got working, unfortunately).

 

Ah, those were the days.  Ironically, my second computer (an AMD 486 DX/2 66MHz) had a 500MB HDD, but only 640KB of RAM.  Yes, a single stick of 640KB EDO SIMM RAM.

[Guest]

Just now, Jito463 said:

But is your wallet ready?

Yes. Yes it s.

[The King of the Undead]

12 minutes ago, Den-Fi said:

Yes. Yes it s.

WHERE DO YOU WORK?!