Rumor: Next gen AMD Epyc to get 64 cores?

[System Error Message]

Just now, leadeater said:

Isn't it currently 3TB ram per EPYC CPU? 3x4 = 12TB ram

depends on the dimm size. It gets to a point where you no longer get a good price/GB of ram.

But with 12TB of 32 channels, you wont even need storage if you have a UPS.

[Dylanc1500]

1 hour ago, Taf the Ghost said:

Yes. It'll be the first design-improved Zen cores. We'll probably know the details of the uplift somewhere in Q4 2018. If AMD is aggressive, and yields are good, they might be able to release the Mainstream Ryzen on Zen 2 in late 2018.

 

Oh, that's probably it. @cj09beira , @leadeater . The Big Zen is for the PCIe 4.0 boards. PCIe 4.0 won't come to Desktop until AM5 &/or Tigerlake, but there is already a use for it in the server space. This would let them make Eypc 2 & Ryzen 2 off the same die package, with "Big Eypc" on PCIe 4.0 with 32c, 48c or 64c. Premium products, but if they get a 10-15% IPC uplift, AVX2 and PCIe 4.0, what's Intel's advantage? That's some murderous amounts of performance in a 2U config.

 

If we think about the Roadmap, PCIe 4.0 was just finalized, though it was effectively done back in Spring, but DDR5 isn't until 2020 (if no delays). AMD, because of the new modular design approach, can just drop in whichever controller they need, however the rest of the tech needs to be there. This is why Zen 3 might follow Zen 2 after just one year. With IPC and design improvements. Zen 3 will have DDR5, which should help keep those CPUs really well fed. 

 

Introducing a "Big Zen" design branch let's AMD really get involved in the server space when Intel is going to have 32c designs as max, but the major key is it lets them adopt the Server space technologies faster. While at the same time letting them run Zen 2+ CPUs out if DDR5 gets delayed. Big Zen allows for more flexibility going forward, and it should thusly be assumed that's likely what is happening.

 

I still think the dies are going to be tiny compared to what we expect. The Big Zen is probably going to be a 200-240 mm² die that they can package in the 4-way cluster. Which is why it's going to be messy for Intel. Their next XCC core is probably around 750 mm² on 14nm++. 

Just a heads up, PCIe 4.0 has already been implemented by IBM and available since roughly late Q1- early Q2 this year. I can't say exactly when.

[Dylanc1500]

12 minutes ago, leadeater said:

Isn't it currently 2TB ram per EPYC CPU? 4x2 = 8TB ram

 

Edit:

Updated to from 3TB to 2TB per CPU

Wait, from what I remembered EPYC only allows dual socket configurations? Or are you guys speaking theoretically?

[Princess Luna]

15 hours ago, D Levy said:

Can windows 10 even use/give access to all 64 of those cores?

Of course it can, it's just pointless as most will idling all the time and the performance on the cores being used single-thread wise will sucks.

[Technomancer__]

15 hours ago, D Levy said:

Because shortly after EPYC gets 64 cores... look out because updated Threadripper using those other two dyes.

 

those dies are fake

there there just to hold the thing together

[XenosTech]

1 minute ago, Ethocreeper said:

those dies are fake

there there just to hold the thing together

At this point it think they're there to make it fit the socket with out needing another pcb attached to it like some of the x299 chips

[Taf the Ghost]

27 minutes ago, Dylanc1500 said:

Just a heads up, PCIe 4.0 has already been implemented by IBM and available since roughly late Q1- early Q2 this year. I can't say exactly when.

Right, first consumer-level PCIe 4.0 products will land in Q3/Q4 2018. But when they hit the motherboards is a different issue. Zen 2 will need PCIe 4.0 anyway for server space, but if they do split into Zen & Big Zen, normal Zen might not need it. We'll see. Given the way they use PCIe lanes in Epyc interconnects, it's an interesting issue.

[Trixanity]

2 hours ago, Taf the Ghost said:

Snip 

I don't see why AM4 can't support PCI-E 4.0.

Sure it'll require you to buy a new board but with the way Zen is laid out, the new processors should be simple drop-in to existing boards but limited to PCI-E 3.0 but fully enabled on a new board.

 

However I agree that DDR5 will be on a new socket but that's probably more to do with no backwards compatibility and the socket is EoL by then anyway. Perhaps in conjunction with PCI-E 5.0 if everything aligns.

 

I don't know AMD's goals with Zen 2. AVX is a glaring problem so it's an obvious issue to tackle and they should. Another is improvements to IF and the latency incurred although I'm guessing there are physical limitations to that part of the equation.

IPC and clock speeds are also fairly obvious; they are behind on both. Supposedly the latter is partially alleviated with 12 nm but it'll be interesting to see how 7 nm behaves.

 

I'm not sure what else they can do to get a leg up on Intel. They have the cores, they have the scalability, they have the PCI-E lanes, they have the production costs

 

Oh I forgot: they need to implement Thunderbolt support. It would be a killer feature especially on mobile.

[Dylanc1500]

28 minutes ago, Taf the Ghost said:

Right, first consumer-level PCIe 4.0 products will land in Q3/Q4 2018. But when they hit the motherboards is a different issue. Zen 2 will need PCIe 4.0 anyway for server space, but if they do split into Zen & Big Zen, normal Zen might not need it. We'll see. Given the way they use PCIe lanes in Epyc interconnects, it's an interesting issue.

As far as consumer level products go, I wish they would put more specific interconnects on consumer products. I was always a huge fan of AGP. It would be awesome to see a interconnect like nvlink (just an example as the mezzanine commector probably wouldn't be the greatest idea for consumers lol) specifically for GPUs, it would allow them to design a connector that could be a more efficient design for graphics cards and board layouts and designs. Right now in the consumer level not many people are actually using much of the I/O available to them with PCIe 3.0. 

 

I suppose we shall see what the future holds.

[Taf the Ghost]

12 minutes ago, Trixanity said:

I don't see why AM4 can't support PCI-E 4.0.

Sure it'll require you to buy a new board but with the way Zen is laid out, the new processors should be simple drop-in to existing boards but limited to PCI-E 3.0 but fully enabled on a new board.

 

However I agree that DDR5 will be on a new socket but that's probably more to do with no backwards compatibility and the socket is EoL by then anyway. Perhaps in conjunction with PCI-E 5.0 if everything aligns.

 

I don't know AMD's goals with Zen 2. AVX is a glaring problem so it's an obvious issue to tackle and they should. Another is improvements to IF and the latency incurred although I'm guessing there are physical limitations to that part of the equation.

IPC and clock speeds are also fairly obvious; they are behind on both. Supposedly the latter is partially alleviated with 12 nm but it'll be interesting to see how 7 nm behaves.

 

I'm not sure what else they can do to get a leg up on Intel. They have the cores, they have the scalability, they have the PCI-E lanes, they have the production costs

 

Oh I forgot: they need to implement Thunderbolt support. It would be a killer feature especially on mobile.

The real reason I suspect PCIe 4.0 won't be until AM5 is pretty much just cost reasons. There's no actual reason to put it on Mainstream until then. However, for TR and Eypc? Different issue. AMD has never said they'll be supporting Threadripper's socket to 2020. That's only AM4, so the more likely scenario is that 2019 sees a new TR & Epyc sockets/chipsets to make sure of the upgrades.

 

As for the Mainstream, it'll be supported, but it's going to be rare to be implemented, I'd assume. Nothing really can use it anyway yet in the consumer space.

[cj09beira]

1 hour ago, Taf the Ghost said:

The real reason I suspect PCIe 4.0 won't be until AM5 is pretty much just cost reasons. There's no actual reason to put it on Mainstream until then. However, for TR and Eypc? Different issue. AMD has never said they'll be supporting Threadripper's socket to 2020. That's only AM4, so the more likely scenario is that 2019 sees a new TR & Epyc sockets/chipsets to make sure of the upgrades.

 

As for the Mainstream, it'll be supported, but it's going to be rare to be implemented, I'd assume. Nothing really can use it anyway yet in the consumer space.

i think they can probably keep the same socket and implement pcie 4 as its mostly a clock per pin increase and ryzen is a soc so it shouldn't be too hard, it would be strange for them to use epyc socket for only ryzen and ryzen refresh as normally servers are updated to keep them running well for longer periods,

pcie 4 would help a bit in things like having more devices while having the same lane amount, and would also enable faster nvme ssds as they are limited to 4x

and also make 10Gb ethernet ports use less lanes which is also good, and might help increase support for them on consumer boards

[Taf the Ghost]

2 minutes ago, cj09beira said:

i think they can probably keep the same socket and implement pcie 4 as its mostly a clock per pin increase and ryzen is a soc so it shouldn't be too hard, it would be strange for them to use epyc socket for only ryzen and ryzen refresh as normally servers are updated to keep them running well for longer periods,

pcie 4 would help a bit in things like having more devices while having the same lane amount, and would also enable faster nvme ssds as they are limited to 4x

and also make 10Gb ethernet ports use less lanes which is also good, and might help increase support for them on consumer boards

Given Ryzen's SoC nature, I'm sure they can put it on Mainstream AM4, but will the motherboard manufacturers want to produce them? It'll be AM4+ more than likely and it might make more sense anyway. We're probably too far out to know if DDR5 is going to be on time.

 

Actually, that does make the most sense. Zen 2 is PCIe 4.0 in general, but simply runs in PCIe 3.0 for AM4. AM4+ is the X570 line in 2019, which will give AMD space if they need to run out a Zen 2+ CPU line in 2020 if DDR5 gets pushed back. Zen 3 ("Milan" on servers) will almost assuredly be the DDR5 transition, but that'll require DDR5 be on time. An official AM4+ will build in space for contingency issues.

 

The issue on the Eypc end of things is the interconnect in the 2U servers. Those run as ports of the PCIe connection. So shifting to PCIe 4.0 is going to come with more than a little work for them. Though 128 lanes of PCIe 4.0 is going to be hilarious.

[cj09beira]

4 minutes ago, Taf the Ghost said:

Given Ryzen's SoC nature, I'm sure they can put it on Mainstream AM4, but will the motherboard manufacturers want to produce them? It'll be AM4+ more than likely and it might make more sense anyway. We're probably too far out to know if DDR5 is going to be on time.

 

Actually, that does make the most sense. Zen 2 is PCIe 4.0 in general, but simply runs in PCIe 3.0 for AM4. AM4+ is the X570 line in 2019, which will give AMD space if they need to run out a Zen 2+ CPU line in 2020 if DDR5 gets pushed back. Zen 3 ("Milan" on servers) will almost assuredly be the DDR5 transition, but that'll require DDR5 be on time. An official AM4+ will build in space for contingency issues.

 

The issue on the Eypc end of things is the interconnect in the 2U servers. Those run as ports of the PCIe connection. So shifting to PCIe 4.0 is going to come with more than a little work for them. Though 128 lanes of PCIe 4.0 is going to be hilarious.

i dont think it will be hard for them to move epyc to pcie 4 even for the interconnect because the language is still the same and they must be talking using the pcie controllers, i do see a side effect of this been the fact that they might be able to reduce the amount of lanes for cpu communications in half and keep the same bandwidth, and so it might even mean the introduction of 4 cpu epyc servers, hmm 64*4*2 cores 

[Taf the Ghost]

3 minutes ago, cj09beira said:

i dont think it will be hard for them to move epyc to pcie 4 even for the interconnect because the language is still the same and they must be talking using the pcie controllers, i do see a side effect of this been the fact that they might be able to reduce the amount of lanes for cpu communications in half and keep the same bandwidth, and so it might even mean the introduction of 4 cpu epyc servers, hmm 64*4*2 cores 

Haha. Great pic.

 

As for 4U servers, the NUMA design they're using in Epyc makes going to 4U a little different. Not sure it'd get the benefit from that.

[cj09beira]

8 minutes ago, Taf the Ghost said:

Haha. Great pic.

 

As for 4U servers, the NUMA design they're using in Epyc makes going to 4U a little different. Not sure it'd get the benefit from that.

well whatever it is they already worked pass that to get to 2cpu servers right?, i am missing something here?

 

[TheCherryKing]

18 hours ago, D Levy said:

Can windows 10 even use/give access to all 64 of those cores?

Yes

[TheCherryKing]

It would be nice to have new Epyc CPU's with 4-Way and 8-Way scalability, Unfortunately, I haven't been able to find any information about that.

[Taf the Ghost]

11 minutes ago, cj09beira said:

well whatever it is they already worked pass that to get to 2cpu servers right?, i am missing something here?

 

Structurally, Epyc 2U is setup like a cube. It puts every Package only 2 hops from another, if you think of a package as a vertex. They'd need to add some bridge and I think it'd be off the Infinity Fabric, at that point. It's quite doable, it's just an entire other branch of design that they'd need to do, and it's still AMD we're talking about here. (Basically, it'd be full NUMA nodes, rather than the hybrid system the 2U does.)

[Tribalinius]

4 hours ago, Taf the Ghost said:

The real reason I suspect PCIe 4.0 won't be until AM5 is pretty much just cost reasons. There's no actual reason to put it on Mainstream until then. However, for TR and Eypc? Different issue. AMD has never said they'll be supporting Threadripper's socket to 2020. That's only AM4, so the more likely scenario is that 2019 sees a new TR & Epyc sockets/chipsets to make sure of the upgrades.

 

As for the Mainstream, it'll be supported, but it's going to be rare to be implemented, I'd assume. Nothing really can use it anyway yet in the consumer space.

I thought we were getting closer to maxing out PCIe 3.0 transfer speed using PCIe storage? That would make sense to move to PCIe 4.0 on mainstream platform, if technology permits, if that's the case. At least, that would be one reason to move to it. Beside, what would be the point for AMD to not push the technology as soon as they can? I don't think cost will be a factor for holding on PCIe 4.0. With the way Ryzen shook things up lately, having PCIe 4.0 as a feature is ground for bragging rights for whoever can bring it first to the market in my opinion. That makes for good marketing "Team X brought PCI 4.0 to the table while you will have to wait 6 months for Team Y to see their implementation. See how we care about our customers!"

Threadripper, being the HEDT platform, should benefit from all they can cram into it from the get go. I would not be surprised to see it on "x499" from the start while Ryzen, I guess the timing would be better for "X570" if, again, technology permits.

[Citadelen]

20 hours ago, wcreek said:

Shit Intel gonna 1 up AMD and release a 128 Core CPU, 256 Threads

 

I hate how two things start sooner and sooner each year:
a.) Holiday stuff

b.) Rumors for the next iteration of something that just came out

To be fair AMD has no choice but to try and push out their next generation as soon as it's ready, they need the consumer confidence and money.

[Falconevo]

19 hours ago, leadeater said:

No problem, as I said anything you can share is great . Always good to get a slightly more unbiased view of things than I can get from say HPE, you don't want to sell me servers lol.

 

Silly question, EVERYTHING of course. Actually seriously though the main things I'm interested in are VM hosting (ESXi), Storage Node performance and scaling and SQL Server performance.

I have some SQL testing due, assuming MSSQL rather than MySQL?  

[leadeater]

7 minutes ago, Falconevo said:

I have some SQL testing due, assuming MSSQL rather than MySQL?  

MSSQL, don't use MySQL much and where we do it's really small stuff.

[leadeater]

8 hours ago, Dylanc1500 said:

Wait, from what I remembered EPYC only allows dual socket configurations? Or are you guys speaking theoretically?

Yea dreaming, would be awesome if EPYC 2 supported quad socket, even if realistically that's pointless and few want it.

[Dylanc1500]

13 minutes ago, leadeater said:

Yea dreaming, would be awesome if EPYC 2 supported quad socket, even if realistically that's pointless and few want it.

Ah that's what I thought, just wanted to make sure I didn't miss something. At this point I wish IBM would bring the power 9 arch to the consumer (PC) market in some way. It would be cool to have another competitor, but a competitor that has a good knowledge within that market outside of "x86".

[Trixanity]

5 minutes ago, Dylanc1500 said:

Ah that's what I thought, just wanted to make sure I didn't miss something. At this point I wish IBM would bring the power 9 arch to the consumer (PC) market in some way. It would be cool to have another competitor, but a competitor that has a good knowledge within that market outside of "x86".

Remember Windows RT? There's your answer.