Intel Core-X Series: Full Specs Revealed

[Trik'Stari]

 

On 7/28/2017 at 6:45 AM, Fonzie92 said:

I respect your views but you need to name me one pro of the x299 platform lol

Depends on your use case scenario.

 

No one is going to buy intel's crap for such little performance improvement at such a high cost, when they can get away with slightly less at a way cheaper price.

[leadeater]

2 hours ago, MageTank said:

They most certainly were ram bandwidth limited. They were using hexa-channel memory at 2666 (127.9GB/s x 1 CPU) vs EPYC's octa-channel 2400 (153.6GB/s x 1 CPU).

 

It should also be noted that Skylake Purely's per-core memory bandwidth was extremely weak, at 12GB/s, vs even Broadwell's 18.5GB/s bandwidth per-core. AMD delivered a massive 27GB/s per core, but suffered a limit of 30GB/s for each quad core CCX. No idea how that will impact specific workloads. 

 

It's a little amusing since a lot of people were talking about how some Ryzen CPUs should have staid in 1 CCX when creating smaller SKUs etc but when it comes to higher end workloads and parallel compute spread as wide as you can across EYPC is better for performance than trying to stuff it all in isolated silos.

 

That's why the 8 core EYPC still uses  all 4 dies, memory bandwidth. Testing the 8, 16, 24 and 32 is going to be very interesting as to when/where that 30GB/s limit comes in. The above tests didn't cover as many configurations as I'd have liked. Where's the 4 threads across sockets test on 2 dies vs 4 dies, where's the 8 thread test across sockets on 2 dies through to 8 dies.

 

Look at that 2 threads different socket test, should EPYC be able to get 120GB/s across the socket using more threads since the dies across sockets are paired and 4 x 30 = 120? Or should it be 240 looking at the 8 thread same socket test? More data points please!

 

The FP tests also didn't do any of the above configuration scenarios.

[MageTank]

5 minutes ago, leadeater said:

It's a little amusing since a lot of people were talking about how some Ryzen CPUs should have staid in 1 CCX when creating smaller SKUs etc but when it comes to higher end workloads and parallel compute spread as wide as you can across EYPC is better for performance than trying to stuff it all in isolated silos.

 

That's why the 8 core EYPC still uses  all 4 dies, memory bandwidth. Testing the 8, 16, 24 and 32 is going to be very interesting as to when/where that 30GB/s limit comes in. The above tests didn't cover as many configurations as I'd have liked. Where's the 4 threads across sockets test on 2 dies vs 4 dies, where's the 8 thread test across sockets on 2 dies through to 8 dies.

 

Look at that 2 threads different socket test, should EPYC be able to get 120GB/s across the socket using more threads since the dies across sockets are paired and 4 x 30 = 120? Or should it be 240 looking at the 8 thread same socket test? More data points please!

 

The FP tests also didn't do any of the above configuration scenarios.

Now, imagine if you will, a world where Zen's IMC is better. Friends of mine have already theorized that the IMC is stronger on these server parts, mostly because they already use multi-rank DIMM's at lower speeds (meaning, they benefit from having several ranks per DIMM, and get a ton of bandwidth efficiency from that alone), but imagine if the IMC itself could handle faster DIMM's and tighter timings at the same time. It would be absolutely insane. Ryzen, from a core standpoint, isn't bad. Yes, the CCX design is... different, but not in a bad way. Improving the IMC, especially with how the CCX interconnect is heavily dependent on ram speed, would probably make a very dramatic difference in how these CPU's perform over all. People are infatuated with wanting higher core clocks for Zen 2.0, but I feel their money would be better spent on a superior memory subsystem. 

 

Now, if we could have both, that would be great, but if we had to choose one over the other, i'll take the faster ram this time around, and stick with the very consistent core clocks we have now with Ryzen. Besides, from every bench I've seen, memory clocks scale much better than CPU core. Quite the opposite when looking at Intel, where core is king for the most part. 

[leadeater]

1 hour ago, MageTank said:

Now, imagine if you will, a world where Zen's IMC is better. Friends of mine have already theorized that the IMC is stronger on these server parts, mostly because they already use multi-rank DIMM's at lower speeds (meaning, they benefit from having several ranks per DIMM, and get a ton of bandwidth efficiency from that alone), but imagine if the IMC itself could handle faster DIMM's and tighter timings at the same time. It would be absolutely insane. Ryzen, from a core standpoint, isn't bad. Yes, the CCX design is... different, but not in a bad way. Improving the IMC, especially with how the CCX interconnect is heavily dependent on ram speed, would probably make a very dramatic difference in how these CPU's perform over all. People are infatuated with wanting higher core clocks for Zen 2.0, but I feel their money would be better spent on a superior memory subsystem. 

 

Now, if we could have both, that would be great, but if we had to choose one over the other, i'll take the faster ram this time around, and stick with the very consistent core clocks we have now with Ryzen. Besides, from every bench I've seen, memory clocks scale much better than CPU core. Quite the opposite when looking at Intel, where core is king for the most part. 

I think you also pointed out that the testing was done on slower 2400 ram where EYPC supports 2666. Server memory is also Registered, maybe that allows for better timings or something. It's been a really long time since RAM and RAM controllers has actually mattered or is been worth looking at.

[AnonymousGuy]

9 hours ago, porina said:

For smaller size workloads then peak performance can be met.

I wonder if you can estimate this. Look up the socket total max current, and divide by the number of power pin pairs.

I estimated that each pin is about 24awg wire, which has about 3A of max current.  Skylake X has 250-ish VCCin pins, so 250 * 3A * 2V is about 1500W.  Just for the sake of safety call it 1000W, which is probably more than you could even cool.  Higher VCCin voltage is going to help us here.

[MageTank]

5 hours ago, leadeater said:

I think you also pointed out that the testing was done on slower 2400 ram where EYPC supports 2666. Server memory is also Registered, maybe that allows for better timings or something. It's been a really long time since RAM and RAM controllers has actually mattered or is been worth looking at.

Yeah, 2400 to 2666 is a 10% difference in peak theoretical memory bandwidth by itself, without even factoring in the boost it gives to the infinity fabric. Ryzen in general seems to never stop scaling with memory frequency (we can't really know the ceiling, due to how poor the IMC is, so about 3866 is where we stop in dual channel, single rank when extremely lucky). 2666 is about as realistic as one can get with 8 channels though, even with good IMC's. Not only that, but one does not simply OC ram on a mission critical environment. That's masochism to an extreme. 

[Taf the Ghost]

1 hour ago, MageTank said:

Yeah, 2400 to 2666 is a 10% difference in peak theoretical memory bandwidth by itself, without even factoring in the boost it gives to the infinity fabric. Ryzen in general seems to never stop scaling with memory frequency (we can't really know the ceiling, due to how poor the IMC is, so about 3866 is where we stop in dual channel, single rank when extremely lucky). 2666 is about as realistic as one can get with 8 channels though, even with good IMC's. Not only that, but one does not simply OC ram on a mission critical environment. That's masochism to an extreme. 

Some of the finer detailed projections have put 4000 the point where you'd be likely not to see any gain from higher memory speed with Ryzen. The uplift beyond 2933 isn't as much as people think. The CCX to CCX calls are double-sided, so dropping the core hop latency gives most of the boost beyond the extra bandwidth. Though you seem to quickly run into other issues once you get it low enough.

[MageTank]

13 minutes ago, Taf the Ghost said:

Some of the finer detailed projections have put 4000 the point where you'd be likely not to see any gain from higher memory speed with Ryzen. The uplift beyond 2933 isn't as much as people think. The CCX to CCX calls are double-sided, so dropping the core hop latency gives most of the boost beyond the extra bandwidth. Though you seem to quickly run into other issues once you get it low enough.

Well, with how limited timings are with Ryzen (even after AGESA 1.0.0.6), the most prominent way to improve latency, is by increasing memory frequency while keeping timings the same. The fact that we can't use rank interleaving without seriously limiting frequency, and also not having access to tREFI, means latency is going to be abysmal no matter what we do. 

 

Give me just a few more timings, and I promise I can tame Ryzen's latency, even on the higher end. I imagine Ryzen will show some pretty significant performance boosts from a reduction in latency.