[Rumour] AMD's Zen To Have Ten Pipelines Per Core

[LukaP]

 

It would PPC 7 if it's 4 threads per core, or just like Intel's Hyperthreading if 2 per core. Power 8 is 8 threads per core, and Power 9 hasn't been released yet.

well i just referenced the newest one because i didnt know the exact numbers of decodes and registers per core of the iterations but i knew they were high

[patrickjp93]

Sez you. Considering you never even provide sources for anything.

 

 

Shared cache is shared cache. And Zen doesn't appear to have much in the way of L2 Cache at all-so it will still be crippled by it.

It has more L2 cache than Skylake, double actually...

http://www.fudzilla.com/news/processors/37494-amd-x86-16-core-zen-apu-detailed

http://techreport.com/review/28751/intel-core-i7-6700k-skylake-processor-reviewed/4

 

My God how does @LukaP stand you people? At least when Opcode and I argued it was over business practices and projections, and the only reason he left was because of a blood feud with one of the mods. 

[patrickjp93]

I understand why you thought it was CMT, i am just saying, this is SMT. If this block is an accurate representation of what we will see in the final product, you shouldn't have to worry. The #1 downfall of CMT was the way the resources were managed. Modularity. Great in theory, not so great in application. 

In coding, modularity is beautiful both in theory and application. Debugging is so much easier when you can separate everything out. That, and compilers tend to optimize better when you have fewer lines per method/function. For Clang the optimal # of lines per function is about 9 unless it's basically doing a list of function calls.

[SurvivorNVL]

If it has four threads per core, then wow.  That would be a feature to keep Zen on the map.

[patrickjp93]

If it has four threads per core, then wow.  That would be a feature to keep Zen on the map.

Except Intel got there first with the Xeon Phi and the socketed KNL chips coming out in...4 months.

[SurvivorNVL]

Except Intel got there first with the Xeon Phi and the socketed KNL chips coming out in...4 months.

So, then if they incorporate that in to Skylake-E with Six-channel memory.. eh, still doesn't look like AMD has a win unless it is in pricing, but then again they're trying to re-establish their image as not being the cheaper option.

[Tech_Dreamer]

& those better be fast unless it's gonna sit there like bulldozer with 8 core was to an i7 with 4 physical cores was performance degradative..

[jos]

any idea why u need AGU.. when it can address 2^64 directy? @patrickjp93

[Humbug]

im hoping we can see it before AMD files for bankruptcy

We will. They have enough money for a few more years I hear.

But if Zen fails then they will not be able to recover, if they are ever going to start making profits again 2016-2017 has to be it.

[Prysin]

We will. They have enough money for a few more years I hear.

But if Zen fails then they will not be able to recover, if they are ever going to start making profits again 2016-2017 has to be it.

even the most pessimistic analysists say 2020-2025 is the "earliest" we can expect AMD to kick the bucket.

If they get some decent cash flow going in, they would easily make it past that.

[patrickjp93]

even the most pessimistic analysists say 2020-2025 is the "earliest" we can expect AMD to kick the bucket.

If they get some decent cash flow going in, they would easily make it past that.

Technically it's 2019 if AMD's cash reserves fall below 600 million USD.

[Humbug]

even the most pessimistic analysists say 2020-2025 is the "earliest" we can expect AMD to kick the bucket.

If they get some decent cash flow going in, they would easily make it past that.

I agree they are not on the verge of shutting down.

But Zen has to be the start of the turnaround for them. When bulldozer failed they still had enough time and resources to spend years of R&D coming up with Zen. If Zen fails they won't have that luxury. 2016-2017 is make or break for them. They are leaner now, have less costs and probably more efficient. They could be profitable if Zen works. As Lisa Su basically admitted the future of the company depends on it.

[Prysin]

Technically it's 2019 if AMD's cash reserves fall below 600 million USD.

yes, due to their debt payment being due late 2019..... however, if they are close to realizing the downpayment figure, some negotiation may get them a quarter or two to gather more funds.

[Prysin]

I agree they are not on the verge of shutting down.

But Zen has to be the start of the turnaround for them. When bulldozer failed they still had enough time and resources to spend years of R&D coming up with Zen. If Zen fails they won't have that luxury. 2016-2017 is make or break for them. They are leaner now, have less costs and probably more efficient. They could be profitable if Zen works. As Lisa Su basically admitted the future of the company depends on it.

their most pressing issue is not directly financial at this point. It is their reputation.

Their reputation is tarnished, worst of all, even with their shitty CMT products, they still could marketed themselves better and sold more. If they had gone all in on "budget" offerings early on, and prioritized quantity heavily over a good "quality" margin, they would have fared better by now.

But lack of marketing, reviewers slaughtering their products and a ever so strong Intel marketing and product line has litterally pulled the plug by now.

 

Even with bulldozer being shit, they HAD a chance to turn around. They just didnt grasp it in time.

[patrickjp93]

yes, due to their debt payment being due late 2019..... however, if they are close to realizing the downpayment figure, some negotiation may get them a quarter or two to gather more funds.

Early 2019, 1st week of January.

[jos]

Early 2019, 1st week of January.

any idea why u need AGU.. when it can address 2^64 directy?

[patrickjp93]

any idea why u need AGU.. when it can address 2^64 directy? @patrickjp93

For virtual memory on databases that well exceeds that number of addresses.

[Humbug]

If they had gone all in on "budget" offerings early on, and prioritized quantity heavily over a good "quality" margin, they would have fared better by now.

What would be the point?

The objective is to make as much money as possible. Not to gain the maximum market share. Reducing your price below a certain point defeats that purpose as your margins become too small to compensate via increased quantity.

[jos]

For virtual memory on databases that well exceeds that number.

it is 2 Exabyte. But will it ever exceed? how many extra bits are they talking about? 

[patrickjp93]

it is 2 Exabyte. But will it ever exceed? how many extra bits are they talking about? 

Probably 16-32 extra bits.

 

Alternatively, the AGU may be useful for address translation between CPU and GPU pointers or for pointers to pointers.

[jos]

Probably 16-32 extra bits.

 

Alternatively, the AGU may be useful for address translation between CPU and GPU pointers or for pointers to pointers.

Reading this i think it is processing 4 ALU and few floating point processing units.. then AGU maybe deciding the next instruction to be fetched as each instruction processing can generate new fetch...It may have nothing to do with addressing length...exceeding 2 Exabyte is useless...adding just 16bit makes it 128 Yottabyte...

[patrickjp93]

Reading this i think it is processing 4 ALU and few floating point processing units.. then AGU maybe deciding the next instruction to be fetched as each instruction processing can generate new fetch...It may have nothing to do with addressing length...exceeding 2 Exabyte is useless...adding just 16bit makes it 128 Yottabyte...

That's usually the job of the TLB (Translation Lookahead Buffer) which is attached to the cache. I'm guessing this is more about trying to shorten the time to do tree/graph traversals and the like.

 

We already have multiple 10s of exabytes in size for some of the world's largest data centers, and we're approaching the era where we can achieve an exa of fata manipulations in a single second. Extending addressing space for virtual memory into yottabytes isn't stupid from Intel's position.

[LukaP]

It has more L2 cache than Skylake, double actually...

http://www.fudzilla.com/news/processors/37494-amd-x86-16-core-zen-apu-detailed

http://techreport.com/review/28751/intel-core-i7-6700k-skylake-processor-reviewed/4

 

My God how does @LukaP stand you people? At least when Opcode and I argued it was over business practices and projections, and the only reason he left was because of a blood feud with one of the mods. 

i dont, i just use *sunshine and rainbows* when im really mad

[Guest Generallee]

 like the voodoo 6000

 

[jos]

That's usually the job of the TLB (Translation Lookahead Buffer) which is attached to the cache. I'm guessing this is more about trying to shorten the time to do tree/graph traversals and the like.

 

TLB is used to speed up virtual memory addressing... it will have a buffer and bypass virtual address generation altogether. Does multi processor require to have same addressing require full addressing space per core then i can see use of exceeding exabyte in multi processor scenario... but for desktop class processor? i have not read about tree traversal much.. BUt is it spanning tree processing in information coding? Isn't its processing parallelism achieved using modified algorithm. i am confused..