AMD Announces Ryzen Embedded V1000 & Epyc Embedded 3000

[Trixanity]

3 minutes ago, The Benjamins said:

Raven and Zeppelin do not have on die 10Gb but these do. I think their are some other small changes.

As I said that could easily just be PCI-E lanes. Ethernet isn't built-in either way (AMD doesn't have the IP). They've just validated and slapped 10Gb onto the reference platform. I mean motherboard vendors already have to slap their ethernet controller of choice on the board (including Intel solutions) and there exists AM4 boards with 5Gb Ethernet.

[Zagna]

17 minutes ago, The Benjamins said:

Raven and Zeppelin do not have on die 10Gb but these do. I think their are some other small changes.

From Zen - Wikichip

• 6 x4 PHYs plus 5 x2 PHYs
  • Support PCIe, WAFL, xGMI (Inter-Chip Global Memory Interconnect), SATA, and Ethernet
    • Ethernet complex: Up to 4 lanes of 10/100/1000 SGMII, or 10GBASE-KR, or 1000BASE-KX Ethernet operation

The 12G PHYs are configurable to some extent.

[Guest]

@PCGuy_5960 I'm interested in your thought on this. Mind posting them?

[leadeater]

3 hours ago, M.Yurizaki said:

An embedded systems CPU is purpose built for the sort of applications with the characteristics I listed above.

 

But I think Epyc Embedded is actually more for microservers, not specialized devices like what the others were saying. Not to say you can't use Epyc Embedded in that field.

I think it's also targeted at software defined networking appliances too.

[leadeater]

2 hours ago, Trixanity said:

As I said that could easily just be PCI-E lanes. Ethernet isn't built-in either way (AMD doesn't have the IP). They've just validated and slapped 10Gb onto the reference platform. I mean motherboard vendors already have to slap their ethernet controller of choice on the board (including Intel solutions) and there exists AM4 boards with 5Gb Ethernet.

Not when the Ethernet controller is inbuilt in to the chipset they don't. What they are saying is the Ethernet processing is done on chip and there are dedicated pin outs from the CPU for it, you might have to still go in to another IC on the motherboard before the actual network port but that doesn't do any actual processing of network traffic.

[GDRRiley]

I see some great micro servers, NAS boxes and routers coming out of this. 

[Trixanity]

8 hours ago, leadeater said:

Not when the Ethernet controller is inbuilt in to the chipset they don't. What they are saying is the Ethernet processing is done on chip and there are dedicated pin outs from the CPU for it, you might have to still go in to another IC on the motherboard before the actual network port but that doesn't do any actual processing of network traffic.

Page refreshed just before posting. When will the forum start saving posts temporarily? I hope I got my post out as intended anyway.

 

Anyway: can you clarify your post? 

 

I can't find any references to Ethernet in Zen anywhere except the previously linked wiki page.

 

If there is a special physical link I would assume it's not bandwidth limited otherwise 5Gb and 10 Gb boards wouldn't exist unless they need to circumvent that link with whatever latency and overhead that may entail.

 

However if the motherboard controllers are dummy chips relaying the signal from the port why do they affect performance so much? Is it just the software stack? It's hard to believe you could otherwise mess up a specification so badly as to incur hundreds of megabit penalities (and other issues).

 

Or are you saying this is a new chip that actually has it built-in as opposed to previous iterations? And that would mean it's serving a market with very sensitive applications. I mean why else spend 10 of millions on getting a new chip out (cost is reduced since the design is mostly the same if this is the case - specifically CPU and GPU)? They're cash strapped as it is so the market must be important for them to pull out all the stops for this.

 

Another question would be what are the penalties for sticking a PCI-E card with NICs on your board in comparison and how does it differ?

[leadeater]

1 minute ago, Trixanity said:

Or are you saying this is a new chip that actually has it built-in as opposed to previous iterations?

This is new, but a bit different and I wasn't quite correct. EPYC and this embedded Ryzen are SoC designs and they are just assigned PCIe lanes for the purposes of connecting to a network controller.

 

On Ryzen and Intel this is normally done off the chipset but that's a real bandwidth bottleneck if you're using dual 10Gb along with other devices like NVMe off the chipset. One of the many reasons why I like TR and EPYC so much, PCIe lanes off the CPU.

 

13 minutes ago, Trixanity said:

Another question would be what are the penalties for sticking a PCI-E card with NICs on your board in comparison and how does it differ?

If delivered off the chipset you're better off using a PCIe card as those lanes are off the CPU so lower latency and not bandwidth sharing. 

[Doobeedoo]

Cool to see them filling so many markets. 

[MyName13]

On 2/21/2018 at 7:43 PM, XenosTech said:

Mostly cost, form factor and tdp. The full sized versions of these will give off a lot more heat

How will they decrease TDP at the same clock rate?Why would it be cheaper than non embedded CPUs?

[XenosTech]

9 minutes ago, MyName13 said:

How will they decrease TDP at the same clock rate?Why would it be cheaper than non embedded CPUs?

Better silicon quality means less voltage to hit the same clocks plus it probably has been tweaked on the arch to meet this target also.

[MyName13]

17 hours ago, XenosTech said:

Better silicon quality means less voltage to hit the same clocks plus it probably has been tweaked on the arch to meet this target also.

For something to be considered embedded, what does it's TDP need to be?Around 25 W maybe?Can they really have such good silicon to decrease the TDP by almost 3 times?

[leadeater]

48 minutes ago, MyName13 said:

For something to be considered embedded, what does it's TDP need to be?Around 25 W maybe?Can they really have such good silicon to decrease the TDP by almost 3 times?

It's just microcode optimization to control the P-States and turbo tables of the CPU to keep it within TDP spec, also TDP isn't power usage. They are setting a target TDP which will limit the single core boost amount and length it boosts along with multi core boost which will be far lower than a higher TDP part even if the listed spec base and boost speeds are the same as those are single core numbers.

 

A CPU core requires a certain amount of watts to archive a given frequency, so if the vcore needs to be 1.2V to get 3.8GHz and requires 25A that's 30W per core. That means on a 65W TDP CPU the most you'll see is 3 cores boosting to 3.8GHz then quickly dropping down to either a lower frequency or the 3rd core will significantly drop while the other two remain higher.

 

The same core might only require 8A to achieve 3Ghz to that's 12W per core or 77W for an 8 core CPU, well within expected power usage of a 65W TDP CPU for all core max boost.

 

All made up numbers of course and I do note the all core boost numbers of the actual products are lower than what I used, but you get the picture.