So theoretically, I've got 32 PCIe lanes I can essentially use then, thanks to the chipset? Or at least that would be my assumption if I were to add the CPU lanes with the chipset ones.
To be precise, there are 28 PCIe lanes connected to three physically x16 slots, that will run at x16/x8/x4 maximum with your CPU.
Then there is a DMI 3.0 connection, with a bandwidth equivalent to 4 PCIe lanes, to a PCH chip. That PCH chip is connected to the x1 slots, the remaining (physically) x16 slot, LAN, SATA ports, M.2 ports, etc. So, you have kind of 4 more lanes there, but those are shared between everything that connects through the PCH. The PCH acts as a switch, so any device can use up to the equivalent of 4 lanes if no other device is using them, but if more than one device connected through the PCH is asking for bandwidth, they'll get less than x4 equivalent.
That may happen even if you have unused "CPU lanes", since those are available only to devices installed in the relevant PCIe slots, and cannot be shifted to the PCH.