Intel Preparing Multiple Hexacore Coffee Lake CPUs

[Drak3]

Just now, TheDankKoosh said:

I understand what speedstep is for, but considering that the 7700hq still has a fairly high base of 2.8 ghz what is the actual point of bringing the clockspeed down that far if the chips are the same tdp? This makes it seem like they are drastically lowering boost speeds as well.

Power efficiency. Mobile processors need that because batteries can't run them indefinitely. Desktop processors, because some people care about power efficiency and thermal management.

Bringing down the base speed allows for just that, and SLX dodeca and up could seriously benefit from it if not soldered, and if soldered, still benefit.

[MageTank]

Just now, TheDankKoosh said:

First, the 8700hq will be worse at holding up power and thermal limits since intel has done next to nothing on 14nm to truly improve efficiency for a full load other than add a few hundred mhz on the same cpu since skylake came out, which will be entirely negated because I guarantee that the 8700hq won't even have the all core max of 3.1 that the 6700hq did have. Speedshift is for switching from low to high loads quickly, and I can deal with a 50ms delay for my 4720hq to ramp up to full speed and stay there.

 

Secondly, I have used both platforms and I don't find a tangible real world difference in either of them, this might be attributed to me being a power user, with most others not being power users like me. 

 

Third, what I'm trying to say is that the low base is most certainly indicative of a low boost as well, and that isn't good since I highly doubt that they have made any tangible ipc gain. Speedshift cannot make clockspeed come out of thin air, therefore if there is no ipc gain then there is actually a decrease in performance except through the programs that use extra cores and threads. 

You are only making assumptions. You have zero reason to believe the boost will be low as a result of the lower base, and no recent patterns exist to confirm that assumption. To speak in absolutes, saying "it will be" worse at holding higher power and thermal limits, is silly. This is Intel's 4th go at 14nm, and many things can be done to improve efficiency without having a die shrink. Leakage has been reduced with each 14nm generation, and efficiency can be improved by doing something as simple as redesigning the pinout of the substrate itself. That was the theory on the desktop coffee lake CPU's, and partly why people assumed it would require an entirely new socket.

 

To assume it's boost will be lower due to it's base being lower, I just don't see the reasoning behind it. If we are to go based off rumors:

This is claiming a 1.6ghz base, 3.4 boost, on a 15w CPU. It's probably safe to assume the larger chips will have a higher base clock. As for why they are going with a lower base...

3 minutes ago, TheDankKoosh said:

I understand what speedstep is for, but considering that the 7700hq still has a fairly high base of 2.8 ghz what is the actual point of bringing the clockspeed down that far if the chips are the same tdp? This makes it seem like they are drastically lowering boost speeds as well.

It makes perfect sense if you consider power efficiency. Having a boost table that wide allows more granular control over the CPU multiplier for the user (the very same control you bragged about having before). While you won't be able to overclock, you have an extremely wide window in which you can underclock (for various power/thermal reasons) along with the ability to use less power when doing mundane tasks. Rather than idle at 800mhz, and boost to your high turbo boost the moment you do something that requires your CPU's higher clock speeds, it can instead boost to a lower "base" frequency and use less power in doing so.

 

For desktop users, we don't really need this, as we can define these speeds on our own with complete control over our BIOS, but this is not the case for laptop users. You have no idea how many people complained about using the XPS13, and being confined to a strict package power limit (CPU + iGPU) of 15W (25W short burst). This means that at any given time, if the CPU required more power, the GPU would throttle, and vice versa. Their only way to allow for the GPU to have enough power for 3d applications, was to use Throttlestop's clock modulation feature, and that was a terrible compromise to make. With a larger turbo window (and hopefully control over the multiplier for underclocking through XTU), they can have fine-grain control over how much power the CPU half of the package can use. 

 

I say we wait until we actually see the chips and their relative performance before we get up in arms, calling it "worse" without knowing. I'd be more inclined to believe if I had some evidence to go with it. 

[juri-han]

coffee lake might have some of the same problems skylake-x has in games more specifically the 7800/7820x, going from ring bus to mesh architecture (hmm that sounds familiar .. almost like glued together CPU dies) not to mention lower clock speeds then a 7700k

 

going from 4 cores to 6 is a good start but it might take awhile for those extra cores to makeup for the drop in speed, honestly quad cores in ultra books or HT in i5s is alot more interesting atm

 

 

[Grinners]

5 hours ago, Drak3 said:

 

If Intel decided to make a highly power efficient version of the 7700K, by reducing the base clock to 2.1GHz and make the boost table go up to that of the 7700K, it'd still be the same chip giving the same performance under the same heavy loads, and only idles lower.

Is this the case? I was under the impression that turbo boost only boosts 1 or 2 of the cores to the max boosted speed. 

 

If this is the case then a base clocked 2.1ghz 7700k with a boost clock of 4.5ghz would be nowhere near a 4.2/4.5ghz 7700k when using 3 or 4 cores. 

[MageTank]

2 hours ago, juri-han said:

coffee lake might have some of the same problems skylake-x has in games more specifically the 7800/7820x, going from ring bus to mesh architecture (hmm that sounds familiar .. almost like glued together CPU dies) not to mention lower clock speeds then a 7700k

 

going from 4 cores to 6 is a good start but it might take awhile for those extra cores to makeup for the drop in speed, honestly quad cores in ultra books or HT in i5s is alot more interesting atm

 

 

Has Coffeelake been confirmed to have that restructured cache? I don't recall seeing it anywhere. In fact, every leak I've seen thus far, still shows it with a large L3 cache. It's unlikely to have the same restructured cache if it's still using a large L3 over a large L2. 

[leadeater]

7 hours ago, VagabondWraith said:

It was pointed out over at overclockers through testing that the 6-8 core do in fact support full AVX512 throughput. @done12many2 & @TahoeDust can confirm this.

Well they have a few AVX512 instructions just not all of them, not even Skylake-SP has all of them.

 

http://www.anandtech.com/show/11550/the-intel-skylakex-review-core-i9-7900x-i7-7820x-and-i7-7800x-tested/3

 

Not actually sure where this no AVX512 stuff came from since Intel was rather forthcoming with information about this.

 

Edit:

And not all the server CPUs have the same AVX makeup either, Skylake-X being based off the 6000 series I believe.

 

 

Edit 2:

Right I see where it's come from:

Quote

Nominally the FMAs on ports 0 and 1 are 256-bit, so in order to drive towards the AVX-512-F these two ports are fused together, similar to how AVX-512-F is implemented in Knights Landing. The six-core and eight-core Skylake-X parts support one fused FMA for AVX-512-F, although the 10-core will support dual 512-bit AVX-512-F ports, which seems to be located on port 5. This means that the 10-core i9-7900X can support 64 SP or 32 DP calculations per cycle, whereas the 8-core/6-core parts can support 32 SP or 16 DP per cycle.

 

[Tiber1337]

Unless I can push those cores easily to 5.0ghz I'm not impressed

[MageTank]

1 hour ago, leadeater said:

Well they have a few AVX512 instructions just not all of them, not even Skylake-SP has all of them.

 

http://www.anandtech.com/show/11550/the-intel-skylakex-review-core-i9-7900x-i7-7820x-and-i7-7800x-tested/3

 

Not actually sure where this no AVX512 stuff came from since Intel was rather forthcoming with information about this.

 

Edit:

And not all the server CPUs have the same AVX makeup either, Skylake-X being based off the 6000 series I believe.

 

 

Edit 2:

Right I see where it's come from:

 

So literally half the bit-ops/clock like I said earlier?

Quote

Nominally the FMAs on ports 0 and 1 are 256-bit, so in order to drive towards the AVX-512-F these two ports are fused together, similar to how AVX-512-F is implemented in Knights Landing. The six-core and eight-core Skylake-X parts support one fused FMA for AVX-512-F, although the 10-core will support dual 512-bit AVX-512-F ports, which seems to be located on port 5. This means that the 10-core i9-7900X can support 64 SP or 32 DP calculations per cycle, whereas the 8-core/6-core parts can support 32 SP or 16 DP per cycle.

 

[leadeater]

3 minutes ago, MageTank said:

So literally half the bit-ops/clock like I said earlier?

Yea, originally I thought all of the Skylake-X was Xeon 6000 based but I forgot about the whole knee jerk TR reaction and 14c+ getting added. I'm still looking for an explanation for the above numbers. Looking at all those Xeon product lines it doesn't even make sense that the 6c and 8c Skylake-X would use a different die to the 10c, that's just weird and seems overly costly.

 

Anyway here's what the applicable AVX512 instruction sets are:

 

Quote

The AVX-512 instruction set consists of several separate sets each having their own unique CPUID feature bit; however, they are typically grouped by supporting processor generation.

F, CD, ER, PF

Introduced with Xeon Phi x200 (Knights Landing) and Xeon E5-26xx V5 (Skylake EP/EX "Purley", expected in H2 2017), with the last two (ER and PF) being specific to Knights Landing.

• AVX-512 Foundation (F) – expands most 32-bit and 64-bit based AVX instructions with EVEX coding scheme to support 512-bit registers, operation masks, parameter broadcasting, and embedded rounding and exception control, supported by Knights Landing and Skylake Xeon
• AVX-512 Conflict Detection Instructions (CD) – efficient conflict detection to allow more loops to be vectorized, supported by Knights Landing^[1] and Skylake X
• AVX-512 Exponential and Reciprocal Instructions (ER) – exponential and reciprocal operations designed to help implement transcendental operations, supported by Knights Landing^[1]
• AVX-512 Prefetch Instructions (PF) – new prefetch capabilities, supported by Knights Landing^[1]

BW, DQ, VL

Introduced with Skylake X.

• AVX-512 Byte and Word Instructions (BW) – extends AVX-512 to cover 8-bit and 16-bit integer operations^[2]
• AVX-512 Doubleword and Quadword Instructions (DQ) – adds new 32-bit and 64-bit AVX-512 instructions^[2]
• AVX-512 Vector Length Extensions (VL) – extends most AVX-512 operations to also operate on XMM (128-bit) and YMM (256-bit) registers^[2]

Maybe the benchmark being used was using AVX512BW?

 

Quote

The byte and word instructions, indicated by the AVX512BW CPUID flag, extend write-masking and zero-masking to support smaller element sizes. The original AVX-512 Foundation instructions supported such masking with vector element sizes of 32 or 64 bits. As a 512-bit vector register could hold at most 16 32-bit elements, a write-mask size of 16 bits was sufficient.

With an instruction indicated by an AVX512BW CPUID flag, a 512-bit vector can hold 64 8-bit elements or 32 16-bit elements, so write masks must be able to hold 64 bits. To support this, two new mask types, __mmask32 and __mmask64 have been introduced, along with additional maskable intrinsics that operate on vectors of 8 and 16-bit elements. For example,

https://software.intel.com/en-us/node/534473

[MageTank]

Just now, leadeater said:

Yea, originally I thought all of the Skylake-X was Xeon 6000 based but I forgot about the whole knee jerk TR reaction and 14c+ getting added. I'm still looking for an explanation for the above numbers. Looking at all those Xeon product lines it doesn't even make sense that the 6c and 8c Skylake-X would use a different die to the 10c, that's just weird and seems overly costly.

 

Anyway here's what the applicable AVX512 instruction sets are:

 

Maybe the benchmark being used was using AVX512BW?

 

https://software.intel.com/en-us/node/534473

This explains a great deal. Thanks for providing that. I had completely neglected that it could have been a different subset of AVX512. 

[Taf the Ghost]

@leadeater

 

The 6c, 8c & 10c designs were worked out a while ago. We'd probably call them "semi-custom" in other contexts as they're designed to be segmented in the first place. The 12c only appeared on Intel's slides early in the year. The 18c only a few months ago. So the 12c was in response to Ryzen 7's Engineering Samples. (Makes sense, even now the 7900X isn't that far afield of the 1800X.) 18c is a "panic" response to Threadripper, which is why they just extended to rebranding Xeons.

 

If they hadn't? X299 would be a catastrophic joke and Intel knows it. X499 or whatever it gets called in 2-3 years will be really, really different.

[tom_w141]

20 hours ago, PCGuy_5960 said:

Unless Intel decides to solder it, but I don't think that this is going to happen

Same small size issue will persist. If they do solder it that would be admitting that they could have soldered Kaby lake.

 

Also your graphs. More likely to be a 0% IPC improvement as Covfefe lake is really just Skylake Refresh Refresh (Or Skylake Refresh 2 if you prefer) and not 5.3GHz because more cores + same process = harder to achieve higher clocks, you should recalculate.

 

(btw not to seem negative just saying those numbers are unrealistic, honestly 6 cores on the mainstream for Intel is great and is long overdue)

[Drak3]

5 hours ago, Grinners said:

Is this the case? I was under the impression that turbo boost only boosts 1 or 2 of the cores to the max boosted speed. 

 

If this is the case then a base clocked 2.1ghz 7700k with a boost clock of 4.5ghz would be nowhere near a 4.2/4.5ghz 7700k when using 3 or 4 cores. 

The advertised turbo boost often only boosts 1 or 2 cores, but there is a boost table that has boost speeds for allcore.

 

And in my example, the only thing that changed between the 7700K and a 2.1GHz base clock counterpart is the base clock. They have the same boost table, meaning that they'll perform the same, provided they both are cooled adequately. The 2.1GHz will just idle down lower when that performance is not needed (on the desktop, Youtube, basic stuff), thus saving power.

[PCGuy_5960]

1 hour ago, tom_w141 said:

Same small size issue will persist. If they do solder it that would be admitting that they could have soldered Kaby lake.

The die won't be as small as Kabylake though

1 hour ago, tom_w141 said:

Also your graphs. More likely to be a 0% IPC improvement as Covfefe lake is really just Skylake Refresh Refresh (Or Skylake Refresh 2 if you prefer) and not 5.3GHz because more cores + same process = harder to achieve higher clocks, you should recalculate.

Yeah, but the 7900X can overclock to the same speeds as the 7800X despite having 4 more cores  And Coffeelake is 14nm++, so I believe that 5.3GHz may be possible.

[tom_w141]

18 minutes ago, PCGuy_5960 said:

7900X can overclock to the same speeds as the 7800X despite having 4 more cores

That in itself is wrong it should do better unless its being limited by something else?

 

18 minutes ago, PCGuy_5960 said:

And Covfefelake is 14nm++,

Probably very little meaning. Maybe a slight efficiency boost but tbh its just a name. They could call it "14nm++ Hyper Gaming Lightning VR Edition" still doesn't mean a whole lot.

 

18 minutes ago, PCGuy_5960 said:

5.3GHz may be possible.

You may be right but I'm near certain there won't be an IPC gain. Until the 10nm process.

[Drak3]

43 minutes ago, tom_w141 said:

That in itself is wrong it should do better unless its being limited by something else?

So long as one can adequately cool the chip, nothing should really stop a higher core chip from reaching the same clocks as a lower core except binning, architecture, and power draw. The 7800X is probably hitting a voltage wall and the 7900X isn't being hindered in systems where it can match those clocks.

[Taf the Ghost]

@tom_w141

 

It should be expected that Coffee Lake will allow for higher delided OCs and any IPC gains would have shown up in Kaby Lake. (Coffee Lake was a "late" edition to the 14nm process, so I'd be super surprised to see anything but utterly minor changes that go with a process change at the same process size.) Subtle changes to many little things could see some 1-3% gains just because of memory system improvements and the like.  Or because of a new chipset.

 

We also don't know where the 6c design is from. If they're re-purposing one of the Xeon designs, things could get "interesting". 

[tom_w141]

10 minutes ago, Taf the Ghost said:

It should be expected that Coffee Lake will allow for higher delided OCs and any IPC gains would have shown up in Kaby Lake. (Coffee Lake was a "late" edition to the 14nm process, so I'd be super surprised to see anything but utterly minor changes that go with a process change at the same process size.)

Pretty much exactly what I'm saying  

[leadeater]

8 hours ago, Taf the Ghost said:

@leadeater

 

The 6c, 8c & 10c designs were worked out a while ago. We'd probably call them "semi-custom" in other contexts as they're designed to be segmented in the first place. The 12c only appeared on Intel's slides early in the year. The 18c only a few months ago. So the 12c was in response to Ryzen 7's Engineering Samples. (Makes sense, even now the 7900X isn't that far afield of the 1800X.) 18c is a "panic" response to Threadripper, which is why they just extended to rebranding Xeons.

 

If they hadn't? X299 would be a catastrophic joke and Intel knows it. X499 or whatever it gets called in 2-3 years will be really, really different.

Still doesn't make a lot of sense for the 6c & 8c to be different to the 10c, all three are originally planned SKUs. Only thing I can think of was Intel wanted to put in yet another dick move to make you want/need to buy the highest SKU, just like in the past by limiting PCIe lanes but now only having one with 2 AVX units. So dumb.

[MageTank]

7 hours ago, PCGuy_5960 said:

The die won't be as small as Kabylake though

Yeah, but the 7900X can overclock to the same speeds as the 7800X despite having 4 more cores  And Coffeelake is 14nm++, so I believe that 5.3GHz may be possible.

Kaby couldn't do 5.3 stable on 99.9% of it's chips. What makes you think it can do that after adding even more cores? I am curious as to what makes you think overclocking gets easier as more cores are added.

 

14 minutes ago, leadeater said:

Still doesn't make a lot of sense for the 6c & 8c to be different to the 10c, all three are originally planned SKUs. Only thing I can think of was Intel wanted to put in yet another dick move to make you want/need to buy the highest SKU, just like in the past by limiting PCIe lanes but now only having one with 2 AVX units. So dumb.

It's 100% an artificial limitation through microcode. Intel has done this in the past, and it makes zero sense for these chips to be a different silicon entirely. 

[PCGuy_5960]

3 minutes ago, MageTank said:

Kaby couldn't do 5.3 stable on 99.9% of it's chips. What makes you think it can do that after adding even more cores? I am curious as to what makes you think overclocking gets easier as more cores are added.

Because it's 14nm++, Skylake was 14nm and most 6700Ks could hit 4.6-4.7GHz. Kabylake is 14nm+ and most 7700Ks can hit 5GHz. This is why I assume that the 8700K will be able to clock slightly higher than Kabylake, but I know that I'll probably be proven wrong 

[MageTank]

Just now, PCGuy_5960 said:

Because it's 14nm++, Skylake was 14nm and most 6700Ks could hit 4.6-4.7GHz. Kabylake is 14nm+ and most 7700Ks can hit 5GHz. This is why I assume that the 8700K will be able to clock slightly higher than Kabylake, but I know that I'll probably be proven wrong 

Skylake was 14nm+. Broadwell was the original 14nm. Need I remind you that with each 14nm step, we got hotter and hotter? Efficiency doesn't come without a cost. That cost tends to be in the form of heat. As things become more efficient (we use more, waste less) heat tends to increase. Kaby is worlds hotter than Skylake, yet tolerates voltage much better and clocks much higher. The same can probably be assumed for Coffeelake. Combine that with the increased core counts, and 5.3ghz starts to look less reasonable.

 

I am not saying 5ghz will be impossible, I just do not expect higher overclocking with more cores, just because it's "more refined". It's simply not the way this works. I would say 5-5.1 will be where people stop on Coffeelake, and that's on a decent setup AFTER a delid. 

[AnonymousGuy]

3 hours ago, MageTank said:

Skylake was 14nm+. Broadwell was the original 14nm. Need I remind you that with each 14nm step, we got hotter and hotter? Efficiency doesn't come without a cost. That cost tends to be in the form of heat. As things become more efficient (we use more, waste less) heat tends to increase. Kaby is worlds hotter than Skylake, yet tolerates voltage much better and clocks much higher. The same can probably be assumed for Coffeelake. Combine that with the increased core counts, and 5.3ghz starts to look less reasonable.

 

I am not saying 5ghz will be impossible, I just do not expect higher overclocking with more cores, just because it's "more refined". It's simply not the way this works. I would say 5-5.1 will be where people stop on Coffeelake, and that's on a decent setup AFTER a delid. 

Skylake was the same process as Broadwell, 14nm.

 

Kaby Lake was 14nm+.  It lowered leakage enabling higher clockspeeds:

 

"more efficiency increases heat" is complete nonsense.  They took the efficiency gained and bumped up clockspeed with it and who knows what happened to the packaging process.  Also don't know the mm^2 of the die so the power density may have gone up a bit with Kaby Lake making it harder to cool.

 

Coffeelake 14nm++ is less of a gain over 14nm+, but still wouldn't be surprised to see easy 5.2Ghz if the heat is under control.

 

[MageTank]

58 minutes ago, AnonymousGuy said:

Skylake was the same process as Broadwell, 14nm.

 

Kaby Lake was 14nm+.  It lowered leakage enabling higher clockspeeds:

 

"more efficiency increases heat" is complete nonsense.  They took the efficiency gained and bumped up clockspeed with it and who knows what happened to the packaging process.  Also don't know the mm^2 of the die so the power density may have gone up a bit with Kaby Lake making it harder to cool.

 

Coffeelake 14nm++ is less of a gain over 14nm+, but still wouldn't be surprised to see easy 5.2Ghz if the heat is under control.

 

Perhaps you simply don't understand how efficiency works. I can demonstrate with AVX if you'd like. When your CPU is being more efficiently used (meaning, nothing is being wasted, every aspect is utilized), it will run hotter as a result.

 

If you think 5.2ghz is going to be "easy" on 6c/12t, you are seriously fooling yourself. Going from Skylake to Kaby Lake, we got 200-300mhz higher on average for overclocking, when core count remained exactly the same. I don't expect this to be the case when you add 2 more cores to it. 

[Grinners]

2 hours ago, MageTank said:

Perhaps you simply don't understand how efficiency works. I can demonstrate with AVX if you'd like. When your CPU is being more efficiently used (meaning, nothing is being wasted, every aspect is utilized), it will run hotter as a result.

 

Heat IS inefficiency. 

 

By definition an increase in heat all else the same is a decrease in efficiency. 

 

Heat is wastage.