Samsung and TSMC Roadmaps: 8 and 6 nm Added, Looking at 22ULP and 12FFC

[Coaxialgamer]

Quote

Samsung and TSMC made several important announcements about the present and future of their semiconductor manufacturing technologies in March. Samsung revealed that it had shipped over 70 thousand wafers processed using its first-generation 10 nm FinFET fabrication process (10LPE) and also announced major additions to its upcoming manufacturing technology roadmap. In particular, the company plans to introduce three processes it has not talked about thus far. TSMC said that it is about to start mass production of ICs (integrated circuits) using its first-gen 10 nm technology and also announced several new processes that will be launched in the coming years, including its first 7 nm EUV process due in 2019.

Samsung said it had started to make SoCs using its 10LPE fabrication technology last October, which is something we already knew. This manufacturing process allowed the company to make its chips 30% smaller compared to ICs made using its 14LPP process as well as reducing power consumption by 40% (at the same frequency and complexity) or increase their frequency by 27% (at the same power and complexity). So far, Samsung has processed over 70 thousand wafers using its 10LPE technology, which can give an idea about Samsung’s 10 nm production capacities (considering that the whole 10 nm production cycle is greater than the 90 days we saw with previous-gen FinFET processes). At the same time, keep in mind that Samsung does not have many 10 nm designs to manufacture right now: we know only of the company’s own Exynos 9 Octa 8895 as well as Qualcomm’s Snapdragon 835 seen in the Samsung Galaxy S8.

 

Quote

As for TSMC, its 10 nm process technology (CLN10FF) is now qualified for production at the company’s GigaFabs 12 and 15, where high-volume ramp is expected to start in H2 2017. Production capacity of these two fabs is hundreds of thousands wafer starts per quarter and TSMC plans to ship 400 thousand wafers processed using its 10 nm manufacturing tech this year. Considering the long production cycles for FinFET-based technologies, it is about time for TSMC to start ramping up 10 nm so to be able to supply enough chips to its main customer in time. Apple is expected to launch its new iPhone products in September or October and needs to get SoCs couple of months before the launch. 

PPA advantages of TSMC’s CLN10FF over its CLN16FF+ (second-gen 16 nm) have been discussed already and they are significant for developers of mobile SoCs (but not that significant for makers of other ICs): a ~50% higher transistor density, a 20% performance improvement at the same power and complexity or a 40% lower power consumption at the same frequency and complexity. Unlike Samsung, TSMC does not seem to plan multiple generations of 10 nm and will go straight to 7 nm next year. 7nm is currently very popular among chip designers, indicating a future major milestone. However, in addition to the CLN7FF, the company will also offer several other manufacturing technologies for ultra-small and ultra-low-power applications.

 

Quote

As noted previously, TSMC’s 7 nm node will be used by tens of companies for hundreds of chips targeting different applications. Initially, the company plans to offer two versions of the manufacturing technology: one for high-performance, and one for mobile applications, both of which will use immersion lithography and DUV. Moreover, eventually TSMC intends to introduce a more advanced 7nm fabrication process that will use EUV for critical layers, taking a page from GlobalFoundries’ book (which is set tp start 7 nm with DUV and then introduces second-gen 7 nm with EUV).

TSMC’s first-generation CLN7FF will enter risk production in Q2 2017 and will be used for over a dozen of tape outs this year. It is expected that high-volume manufacturing (HVM) using the CLN7FF will commence in ~Q2 2018, so, the first “7-nm” ICs will show up in commercial products in the second half of next year. When compared to the CLN16FF+, the CLN7FF will enable chip developers to shrink their die sizes by 70% (at the same transistor count), drop power consumption by 60% or increase frequency by 30% (at the same complexity).

The second-generation 7 nm from TSMC (CLN7FF+) will use EUV for select layers and will require developers to redesign EUV layers according to more aggressive rules. The improved routing density is expected to provide ~10-15-20% area reduction and enable higher performance and/or lower power consumption. In addition, production cycle of such chips will get shorter when compared to ICs made entirely using DUV tools. TSMC plans to start risk production of products using its CLN7FF+ in Q2 2018 and therefore expect HVM to begin in H2 2019.

As it turns out, all three leading foundries (GlobalFoundries, Samsung Foundry and TSMC) all intend to start using EUV for select layers with their 7 nm nodes. While ASML and other EUV vendors need to solve a number of issues with the technology, it looks like it will be two years down the road before it will be used for commercial ICs. Of course, certain slips are possible, but looks like 2019 will be the year when EUV will be here.

Quote

Officially, Samsung says that both technologies will offer “greater scalability, performance and power advantages when compared to existing process nodes,” which obviously means that they are across the board better than Samsung’s current-gen 14 nm and 10 nm offerings. What is important is that Samsung also says that the “8 nm and the 6 nm will inherit all innovations from the latest 10 nm and the 7 nm technologies” respectively. This means that the 8 nm is set to keep using DUV and multi patterning (triple patterning or even quad patterning to be exact, but Samsung has not confirmed usage of the latter) for critical layers, whereas the 6 nm will come after 7 nm and will be Samsung’s second-generation EUV technology.

The only thing that Samsung confirms about its 8LPP manufacturing technology right now is the fact that this is a DUV-based process technology designed to shrink die size (i.e., increase transistor density) and frequency compared to the 10LPP fabrication process. Given the name of the technology and its key advertised advantages over direct predecessor, it is highly likely that the 8LPP will be used to make high-performance SoCs in 2019.

Since Samsung plans to start risk production using the 7LPP in the second half of 2018, the technology is hardly going to be used for high-volume manufacturing before the second half of 2019. Keeping in mind that Samsung now begins HVM using its leading-edge process technologies in October, it is possible that it is going to kick-off 7LPP HVM in fall 2019, but the 8LPP will be Samsung’s most advanced process technology for the better part of the year. Samsung does not mention timeframes for its 6 nm process technology and what to expect from it, but it is logical to assume that it will require more layers to be processed using ASML's EUV tools (like the NXE:3350B pictured above) in a bid to provide PPA advantages and it not be used for high-volume manufacturing before late 2020.

In March, Samsung only made brief announcements regarding its 10LPU, 8LPP and 6 nm process technology without disclosing their exact specifications or even PPA improvements targets. The addition of at least two more DUV technologies (the 10LPU and the 8LPP) in general may indicate that EUV may not be the best choice for all applications in 2019 – 2021, which is perfectly logical. Then again, we do not know how DUV and EUV technologies will co-exist early in the EUV era.

Quote

Not Everyone Needs Leading Edge: TSMC’s 22 nm ULP, 12 nm FFC and 12 nm FFC+

Now let’s discuss something less advanced, but what is required for hundreds of millions of devices sold every year.

Development of FinFET-based chips is more expensive of ICs featuring planar transistors and their manufacturing is more costly as well. As a result, FinFET is virtually unavailable for many smaller designers of SoCs that usually build various solutions for emerging IoT applications. GlobalFoundries and Samsung offer their FD-SOI manufacturing processes to such companies (and these technologies have a number of other advantages in addition to being more cost-effective), whereas TSMC intends to introduce its new 22 nm ULP technology aimed at such applications. The CLN22ULP is an optimized version of the company’s 28 nm HPC+ (high-performance compact plus) manufacturing process that has been available for a while. The 22ULP offers a 10% area reduction and either a 15% performance improvement over the 28HPC+ process, or a 35% power drop. The 22ULP process joins a family of other ultra-low-power processes offered by TSMC and will compete against GlobalFoundries 22FDX as well as Samsung’s 28 nm FD-SOI offering.

Next up is TSMC’s 12 nm FFC manufacturing technology, which is an optimized version of the company’s CLN16FFC that is set to use 6T libraries (as opposed to 7.5T and 9T libraries) providing a 20% area reduction. Despite noticeably higher transistor density, the CLN12FFC is expected to also offer a 10% frequency improvement at the same power and complexity or a 25% power reduction at the same clock rate and complexity. Further down the road, TSMC also plans to offer a ULP version of the CLN12FFC with reduced voltage, but that is going to happen only in 2018 or 2019.

 

Sorry for the long post, but there was so much to cover from the article and i felt this needed to be covered. 

I'm really rooting for the low cost, very low power technologies such as fd soi. 

Sure, the bleeding edge finfet stuff is sexy and all, but it's expensive. Cost for designing and manufacturing chips are going through the roof, and stuff like iot needs to be cheap and reliable in order to be adopted. 

 

Source :http://www.anandtech.com/show/11337/samsung-and-tsmc-roadmaps-12-nm-8-nm-and-6-nm-added/4

[themctipers]

Pictures not embedding. 

[Coaxialgamer]

1 minute ago, themctipers said:

Pictures not embedding. 

They work fine on my end, even on a separate device. Sure it isn't an issue on your end? 

[LukaH]

ok ok but how does this compare to intel as in "real nm" size?

[2FA]

2 hours ago, LukaH said:

ok ok but how does this compare to intel as in "real nm" size?

The size doesn't really matter all too much in actuality as long as it consistently gets smaller, barely anything on the die will end up being the minimum size. If you really care that much, it's usually a difference of 5-7nm or somewhere around there. 

[Doobeedoo]

Ok nice, steady pace to that nm shrinkage.

[LukaH]

10 hours ago, DeadEyePsycho said:

The size doesn't really matter all too much in actuality as long as it consistently gets smaller, barely anything on the die will end up being the minimum size. If you really care that much, it's usually a difference of 5-7nm or somewhere around there. 

It's not that i "care" i was just interested. kinda wish they would do the AMD thing 10nm+ (15nm actually)

[yian88]

17 hours ago, LukaH said:

ok ok but how does this compare to intel as in "real nm" size?

Stop comparing with intel as if they are the only real "nm" tehnology lords, how do you even know intels 14nm is actually 14nm to begin with? what matters with process tehnology is not to compare intels tech to everyone else, but to compare each fab previous process with the newer one, example TSMC 14-16nm FFet versus TSMC 10nm, if the 10nm tech is actually smaller and allows those big gains 30-40% smaller, 30-40% less power then that 10nm TSMC node is real and its great. By comparing with intel you are just being picky intel fanboy and ignore the real information, the fact that the new 10nm tech its actually a lot better than previous 14-16nm and that is all that matters.

[LukaH]

1 hour ago, yian88 said:

Stop comparing with intel as if they are the only real "nm" tehnology lords, how do you even know intels 14nm is actually 14nm to begin with? what matters with process tehnology is not to compare intels tech to everyone else, but to compare each fab previous process with the newer one, example TSMC 14-16nm FFet versus TSMC 10nm, if the 10nm tech is actually smaller and allows those big gains 30-40% smaller, 30-40% less power then that 10nm TSMC node is real and its great. By comparing with intel you are just being picky intel fanboy and ignore the real information, the fact that the new 10nm tech its actually a lot better than previous 14-16nm and that is all that matters.

wow guy take it easy.... it was a simple question out of curiosity i didn't claim that anyone was a lord of anything just wanted to know how close they are.

[Misanthrope]

Honest questions: Who do this guys fabric for in the PC side? I honestly forgot and want to know if AMD or Nvidia would benefit from this

[Trixanity]

1 hour ago, yian88 said:

Stop comparing with intel as if they are the only real "nm" tehnology lords, how do you even know intels 14nm is actually 14nm to begin with? what matters with process tehnology is not to compare intels tech to everyone else, but to compare each fab previous process with the newer one, example TSMC 14-16nm FFet versus TSMC 10nm, if the 10nm tech is actually smaller and allows those big gains 30-40% smaller, 30-40% less power then that 10nm TSMC node is real and its great. By comparing with intel you are just being picky intel fanboy and ignore the real information, the fact that the new 10nm tech its actually a lot better than previous 14-16nm and that is all that matters.

Both yes and no.

You should compare it to previous nodes of the same company but you should also compare it to different companies otherwise you are only holding a company up against itself. That's a pretty poor scenario. That's like only comparing AMD graphics cards against previous AMD graphics cards. See the problem?

 

Since these companies have decided to rely on arbitrary x nm marketing, they should be held accountable for that. Why? Because it's clear as day that not all 14 nm process nodes are created equal - not even close. So are we just gonna ignore that? That seems to be your wish.

 

So either companies start listing actual numbers and quit the marketing BS or we continue to compare node sizes to determine what 14 nm or 10 nm actually means. It's become increasingly evident that silicon can act very differently even on similar nodes depending on who manufactured it so it's important to shed light on that. 

[Trixanity]

1 minute ago, Misanthrope said:

Honest questions: Who do this guys fabric for in the PC side? I honestly forgot and want to know if AMD or Nvidia would benefit from this

TSMC manufactures Nvidia chips.

AMD previously used TSMC (28 nm) for GPU but right now uses Global Foundries for both CPU and GPU but on tech licensed from Samsung.

It remains to be seen whether AMD intends to manufacture Vega or Navi at GloFo or if they intend to switch back to TSMC as it kinda seems like they would be better off doing that.

[Coaxialgamer]

1 hour ago, Misanthrope said:

Honest questions: Who do this guys fabric for in the PC side? I honestly forgot and want to know if AMD or Nvidia would benefit from this

Samsung has made chips for nvidia and amd (samsung particularly in regards to memory). 

Tsmc makes basically every nvidia product and makes many amd products as well ( the 28nm gcn cards come to mind, among others). They make the ps4/xbox/switch soc

[Coaxialgamer]

1 hour ago, Trixanity said:

TSMC manufactures Nvidia chips.

AMD previously used TSMC (28 nm) for GPU but right now uses Global Foundries for both CPU and GPU but on tech licensed from Samsung.

It remains to be seen whether AMD intends to manufacture Vega or Navi at GloFo or if they intend to switch back to TSMC as it kinda seems like they would be better off doing that.

Seeing the put quite a bit of money into the WSA a few months ago, it seems they don't intend to switch any time soon, quite the contrary (amd is gloflo's main customer, so they can tailor the process to their needs. Tsmc has many clients, and they can't be as flexible)

[Coaxialgamer]

1 hour ago, Trixanity said:

Both yes and no.

You should compare it to previous nodes of the same company but you should also compare it to different companies otherwise you are only holding a company up against itself. That's a pretty poor scenario. That's like only comparing AMD graphics cards against previous AMD graphics cards. See the problem?

 

Since these companies have decided to rely on arbitrary x nm marketing, they should be held accountable for that. Why? Because it's clear as day that not all 14 nm process nodes are created equal - not even close. So are we just gonna ignore that? That seems to be your wish.

 

So either companies start listing actual numbers and quit the marketing BS or we continue to compare node sizes to determine what 14 nm or 10 nm actually means. It's become increasingly evident that silicon can act very differently even on similar nodes depending on who manufactured it so it's important to shed light on that. 

Well the thing is, density itself isn't really the biggest concern anymore. 

Cost is more and more determined by the process itself (mask count, patterning) and less by the die size, to a certain extent. Most designs don't push density or die size. 

Power and cost, as well as performance are more important factors. 

 

I'd argue that the minimum feature size isn't really as important anymore. Power density is getting so high that power and leakage is far more important. A smaller die on a given node won't necessarily be cheaper than a larger die on a similar process by another company anymore. 

 

The only designs that really benefit from the small density increases (in logic) are large ASIC/GPU that reach the reticle limit. 

 

Because dennard scaling broke down, smaller transistors don't necessarily mean less power, and it often means more expensive. 

[Trixanity]

3 minutes ago, Coaxialgamer said:

Seeing the put quite a bit of money into the WSA a few months ago, it seems they don't intend to switch any time soon, quite the contrary (amd is gloflo's main customer, so they can tailor the process to their needs. Tsmc has many clients, and they can't be as flexible)

Yes, they changed the agreement so that AMD can have more flexibility in who manufactures their chips. They have a minimum number of wafers required but they made it so that they can use other fabs and pay a fine if they don't meet minimum requirement. GloFo has AMD by the balls, sadly. Sure, it might be AMD's best bet for chip manufacturing in general but not having the freedom to use the best possible fab for the job without having to pony up is a very bad position to be in. 

 

TSMC seems to have the better fab for high performance GPUs. Whether that's true or not is hard to determine since we're also looking at very different chip designs that play a huge role in how a chip behaves but it does seem like, for example, that AMD has a very low clock speed ceiling.

[Coaxialgamer]

4 minutes ago, Trixanity said:

Yes, they changed the agreement so that AMD can have more flexibility in who manufactures their chips. They have a minimum number of wafers required but they made it so that they can use other fabs and pay a fine if they don't meet minimum requirement. GloFo has AMD by the balls, sadly. Sure, it might be AMD's best bet for chip manufacturing in general but not having the freedom to use the best possible fab for the job without having to pony up is a very bad position to be in. 

 

TSMC seems to have the better fab for high performance GPUs. Whether that's true or not is hard to determine since we're also looking at very different chip designs that play a huge role in how a chip behaves but it does seem like, for example, that AMD has a very low clock speed ceiling.

I don't think the low clocks on gcn is really a process issue, rather it's an architectural limitation.

Every 28nm gcn gpu from amd was made on the same 28nm tsmc process as maxwell and kepler, which reached higher clocks. 

 

The gtx 1050 series was made on the same 14nm LPP process as polaris, yet can reach similar clocks to the 16nm pascal cards. 

 

Even ryzen sees clocks near 4ghz, on the same process as polaris. 

I think the clock speeds on gcn is mostly due to the architecture and high power density in general (they pack more transistors per mm² than kepler/maxwell/pascal)

[Trixanity]

3 minutes ago, Coaxialgamer said:

Well the thing is, density itself isn't really the biggest concern anymore. 

Cost is more and more determined by the process itself (mask count, patterning) and less by the die size, to a certain extent. Most designs don't push density or die size. 

Power and cost, as well as performance are more important factors. 

 

I'd argue that the minimum feature size isn't really as important anymore. Power density is getting so high that power and leakage is far more important. A smaller die on a given node won't necessarily be cheaper than a larger die on a similar process by another company anymore. 

 

The only designs that really benefit from the small density increases (in logic) are large ASIC/GPU that reach the reticle limit. 

 

Because dennard scaling broke down, smaller transistors don't necessarily mean less power, and it often means more expensive. 

That's all well and good but doesn't detract from the fact that it's bad practice to only look at what X company does and not compare it to competitors nor does it account for the fact that we do see companies spout nonsense about their nm process when in reality it's a number pulled out of nowhere but is somehow supposed to be better than the competition even if it isn't in fact better (but hey, the number is lower).

 

Essentially what you're saying is that the nm BS doesn't matter but that's kind of the whole point here. The nm changes based on what marketing department decides, not what the actual product is like. So you're not really disagreeing at all even though your comment is reminiscent of a disagreement; in fact you proved my point in a very roundabout way.

[Coaxialgamer]

5 minutes ago, Trixanity said:

That's all well and good but doesn't detract from the fact that it's bad practice to only look at what X company does and not compare it to competitors nor does it account for the fact that we do see companies spout nonsense about their nm process when in reality it's a number pulled out of nowhere but is somehow supposed to be better than the competition even if it isn't in fact better (but hey, the number is lower).

 

Essentially what you're saying is that the nm BS doesn't matter but that's kind of the whole point here. The nm changes based on what marketing department decides, not what the actual product is like. So you're not really disagreeing at all even though your comment is reminiscent of a disagreement; in fact you proved my point in a very roundabout way.

I didn't disagree with your comment. I just brought my input. Sorry if i sounded aggressive about it.