AMD "capsaicin" event at GDC-AMD launches the Radeon Pro Duo(FuryX2)

[SurvivorNVL]

Just now, patrickjp93 said:

Broadwell E launches in April. 

Thank god.  Think that it'll be June for AMD and nVidia's new cards?  I might just grab a Fury Nitro.  Really wish OCZ's damn 1TB Revodrive 400 was out as well.  Hopefully April is the month of releases.

[Prysin]

2 minutes ago, patrickjp93 said:

Broadwell E launches in April. 

Wasnt that 10 core for consumers and 22 for xeons?

[SurvivorNVL]

Just now, Prysin said:

Wasnt that 10 core for consumers and 22 for xeons?

Yeah.  6900k 8-core at $650.  10-core at $1000.  22 becoming the new max.  Or was it 24?

[SurvivorNVL]

Yep.  As per pcper - http://www.pcper.com/news/Graphics-Cards/AMDs-Raja-Koduri-talks-moving-past-CrossFire-smaller-GPU-dies-HBM2-and-more

Arctic Islands will use HBM1.   HBM2 will be on Vega in 2017.  So, GDDR5X, and HBM1 for this year on AMD.  nVidia may beat them to the punch with Samsung HBM2.  This'll shape up to be interesting.

[SurvivorNVL]

@patrickjp93 @Prysin  Y'know if Navi is stated to have a next-generation memory interface after Vega using HBM2 - I bet, or want to take a bet that it is HMC.  Is there anything other than HMC that they could take advantage of?  I know HMC has drastically lower latency to HBM2, a mid-way of bandwidth between HBM1 and 2, etc.

[Tic-Tac]

3 hours ago, patrickjp93 said:

Broadwell E launches in April. 

Where did you get that info? 

 

Also, Polaris and Pascal.... Any chance we will see then this year??? Personally, I really don't care about HBM2, GDDR5X will still be fine as long as they are at least 30% faster than current non-reference 980Ti.  That means smooth ultra 2K gaming easily. 

[DocSwag]

8 hours ago, Jahramika said:

No new Polaris and Pascal will have new DP that has been confirmed already

Polaris and Pascal will have DP 1.3 not DP 1.4. On the Reddit AMA the guy confirmed Polaris has DP 1.3 you can't just implement a new standard within a few months the GPUs were already designed when they released and announced DP 1.4 you can't just go back and change the architecture to support it.

[patrickjp93]

6 hours ago, SurvivorNVL said:

@patrickjp93 @Prysin  Y'know if Navi is stated to have a next-generation memory interface after Vega using HBM2 - I bet, or want to take a bet that it is HMC.  Is there anything other than HMC that they could take advantage of?  I know HMC has drastically lower latency to HBM2, a mid-way of bandwidth between HBM1 and 2, etc.

@Prysin Actually the current HMC spec (as in the next-gen product) has higher bandwidth than HBM2 at 320GB/s per stack.

[patrickjp93]

4 hours ago, Tic-Tac said:

Where did you get that info? 

 

Also, Polaris and Pascal.... Any chance we will see then this year??? Personally, I really don't care about HBM2, GDDR5X will still be fine as long as they are at least 30% faster than current non-reference 980Ti.  That means smooth ultra 2K gaming easily. 

The midrange products (both companies are leading with 250mm sq. and lower sized dies) will use GDDR5 and should be out in June and July.

 

A colleague of mine has an engineering sample of the 6900K. We put it through its paces last night after my Glee Club's concert.

[patrickjp93]

7 hours ago, SurvivorNVL said:

Yeah.  6900k 8-core at $650.  10-core at $1000.  22 becoming the new max.  Or was it 24?

 

7 hours ago, Prysin said:

Wasnt that 10 core for consumers and 22 for xeons?

10 cores for consumers, 22 cores on E5, and 24 on E7.

[Tic-Tac]

Just now, patrickjp93 said:

A colleague of mine has an engineering sample of the 6900K. We put it through its paces last night after my Glee Club's concert.

And the results are? 

[patrickjp93]

18 minutes ago, Tic-Tac said:

And the results are? 

About 10% up in Cinebench as expected (average of 5 runs stock speed for all the following tests). Linpack aggregate is 6.5% up, though interestingly the integer tests improved 12% on average whereas floating didn't really budge despite the uptick in clockspeed over the 5960X. Between 5 and 10% across the Phoronix Suite. Then I did a few custom benchmarks of my own to test singleton floating point, FMA, and vectorized floating point using an arcsine integration to calculate Pi for 4 billion steps. Vectorized had only as much improvement as clockspeed over the 5960X, but singleton FMA was 12% faster (so some IPC improvement). Regular singleton was negligibly faster than just the clockspeed boost allowed. We even did a test to see if Intel had improved its inter-cache communication to deal with false sharing. Solid 25% improvement. I can post the code for the FMA-based integrator and the false-sharing tester if you'd like (though give me 25 minutes to get to campus lol).

 

We thrashed the instruction cache using overly aggressive loop unrolling on a small-form block matrix multiplication. That had a 15% improvement, so the TLB saw some upgrades over Haswell. Then we modified it to take advantage of good caching using a larger (200x200) matrix. 17% improvement.

 

Memory and all else is the same, so we didn't do other system-level tests. And this wasn't all we did, but that covers most of it.

[Tic-Tac]

That is interesting indeed. Any games benchmarks?

[patrickjp93]

2 minutes ago, Tic-Tac said:

That is interesting indeed. Any games benchmarks?

Didn't have time. The concert ended at 9, so accounting for getting out of tuxes to go get food and cool off, then do all the testing switching between the Haswell and Broadwell platform (and swapping the ram between the systems as we went), it was 12:30 when we got done with what we had. And Linpack takes about 20 minutes to run even if you cut out the heterogeneous benchmarks. That, and we both don't game much these days because being seniors and grad students is time consuming enough as it is.

[Tic-Tac]

Just do a games benchmark for the sake of The Internet. If you catch some time of course.

[dimitriianghelov]

22 hours ago, DocSwag said:

I know I already posted a topic on this. That thread will be the one about the event, and I will make this one the one about all the info that comes out. Chances are we will get a ton of info from Capsaicin so I didn't want to throw all the info onto that thread since that would make it the biggest thread ever that will take forever to read, so instead I am making this one so you won't need to read as much.

In case you don't know what I am talking about:

 

Here's a little refresher:

• AMD is hosting an event they call "capsaicin" at GDC (Game Developer's Conference) Monday March 14, 2016 (today as of March 14) at 4:00 P.M.
• They have already teased that they will be showing off Polaris there, and we could glean some purty cool info about Polaris from this
• It is highly rumored that AMD will launch the FuryX2, especially since both the vive and rift went on preorder recently and AMD said they were lining up the launch with the launch of VR headsets
• I think that's it (correct me if wrong)

Also there have some rumors flying around that they will call the FuryX2 the Radeon Duo Pro, though I would take it with a grain of salt

As well, this is pretty recent, but: http://wccftech.com/amd-polaris-10-gpu-vr-demo-gdc-2016/

It seems they will be presenting Polaris 10

EDIT: Forgot to mention they will be demoing it with a SteamVR benchmark. If they are doing that, it sounds to me like it will be a VR Ready part, and we know that Polaris 11>Polaris 10 and Polaris 11 will be about a 232 mm² part, so if you ask me that sounds like some pretty amazing hardware. Only time will tell.

 

[LAST UPDATE: March 14, 2016@5:14P.M. Pacific Time]I will be posting everything we learn here:

• AMD launched the dual Fiji monster, and it's called the radeon pro duo, and costs 1500 dollars! It is water cooled with a 120mm rad. It has 3 8pin pcie connectors and has 16 teraflops of compute power.
• That GPU demoed at CES was Polaris 10. Polaris 10 and 11 will be launching this year, and Vega will be coming next year with HBM2. In 2018 we will be getting Navi
• It is not certain what memory Polaris will get, though amd seemed to be saying Vega will be the first with hbm2 so it might have ggdr5/x or hbm-
• Amd has said Navi will have "next gen memory"...  Something even more revolutionary than HBM? Sounds interesting..... As well,  they said it will have a extremely scalable architecture... Crap now I'm gonna be on the hook for another two years

 

Amd hinted in a interview that they are not gonna use hbm2 yet because it's way to expensive for mainstream , also dual  gpus might become the norm in a few years the same way multi core cpus have become

[dalekphalm]

1 hour ago, dimitriianghelov said:

 

Amd hinted in a interview that they are not gonna use hbm2 yet because it's way to expensive for mainstream , also dual  gpus might become the norm in a few years the same way multi core cpus have become

Fiji might have just been an experiment to see if it was viable. I hope they don't hold back the flagship GPU's because of it - if HBM2 isn't ready, then just use GDDR5X instead. We do not want flagship GPU's with 4GB VRAM max again. Even though the Fury X holds up pretty well, people still lost their shit because it only had 4GB of VRAM.

[MEC-777]

PCper Interview with Raja.

 

 

 

[MEC-777]

8 minutes ago, dalekphalm said:

Fiji might have just been an experiment to see if it was viable. I hope they don't hold back the flagship GPU's because of it - if HBM2 isn't ready, then just use GDDR5X instead. We do not want flagship GPU's with 4GB VRAM max again. Even though the Fury X holds up pretty well, people still lost their shit because it only had 4GB of VRAM.

Indeed. I see nothing wrong with them going to GDDR5x on the Polaris flagships if it keeps the cost down and speeds up. People need to understand that these standards take time to change and implement on a wide scale. HBM, die shrink, etc. we're seeing the first major changes in GPU tech in a long time and it will take some time yet to bring it to market. 

 

That interview with Raja, maybe there's a hint that we could see single cards in the future with multiple GPU dies on-board, but not necessarily in a crossfire config, but more like a multi-CPU implementation. This could be the future of GPUs. I'm speculating of course, but makes sense based on what he said.

[dalekphalm]

19 minutes ago, MEC-777 said:

Indeed. I see nothing wrong with them going to GDDR5x on the Polaris flagships if it keeps the cost down and speeds up. People need to understand that these standards take time to change and implement on a wide scale. HBM, die shrink, etc. we're seeing the first major changes in GPU tech in a long time and it will take some time yet to bring it to market. 

 

That interview with Raja, maybe there's a hint that we could see single cards in the future with multiple GPU dies on-board, but not necessarily in a crossfire config, but more like a multi-CPU implementation. This could be the future of GPUs. I'm speculating of course, but makes sense based on what he said.

I read some speculation in the comments that AMD might have just found a way to use more than 4 stacks of HBM1 on a chip, as well. Perhaps putting 6 or even 8 stacks of 1GB chips total.

 

It's an interesting idea, and I'm curious to see if 4x1GB stacks were a design choice, or a design limitation.

[MEC-777]

8 minutes ago, dalekphalm said:

I read some speculation in the comments that AMD might have just found a way to use more than 4 stacks of HBM1 on a chip, as well. Perhaps putting 6 or even 8 stacks of 1GB chips total.

 

It's an interesting idea, and I'm curious to see if 4x1GB stacks were a design choice, or a design limitation.

I'm guessing it was probably a design and time limitation in getting Fiji into production. R&D as well as manufacturing costs probably played a role as well. 

[Jahramika]

57 minutes ago, dalekphalm said:

I read some speculation in the comments that AMD might have just found a way to use more than 4 stacks of HBM1 on a chip, as well. Perhaps putting 6 or even 8 stacks of 1GB chips total.

 

It's an interesting idea, and I'm curious to see if 4x1GB stacks were a design choice, or a design limitation.

I do not think the memory standard that is in place allows for more than 4 stacks

[Jahramika]

4 hours ago, DocSwag said:

Polaris and Pascal will have DP 1.3 not DP 1.4. On the Reddit AMA the guy confirmed Polaris has DP 1.3 you can't just implement a new standard within a few months the GPUs were already designed when they released and announced DP 1.4 you can't just go back and change the architecture to support it.

Um ya 1.3 not 1.2 is what I was meaning. Ya 1.4 is down the road.

[dalekphalm]

Just now, Jahramika said:

I do not think the memory standard that is in place allows for more than 4 stacks

Unless you can provide a source, I think that's entirely speculation by all parties. It could be that they only had time to develop a memory controller that could handle 4 stacks when they were rushing Fiji out the door.

[Jahramika]

3 minutes ago, dalekphalm said:

Unless you can provide a source, I think that's entirely speculation by all parties. It could be that they only had time to develop a memory controller that could handle 4 stacks when they were rushing Fiji out the door.

You just cant add more interposer connection points to Fiji. I guess Polaris could have more connection points.

 

Interesting, but Nvidia will be using Micron's memory cubes, which specwise do look quite different.