Is AMD FX 8350 really octa core?

[Harshith Mohan]

As the title said.. is it really octa core or is it 4 physical cores and 2 logical cores per physical core?

[Askew]

It is 4 pairs of modules, in each pair one module performs one type of task and the other performs another.

 

It is better to refer to AMD FX chips as '8 thread' rather than '8 core'.

 

Have a look here to gain a better understanding, your chip is 'Piledriver' architecture, but the whole modular core concept is carried over from 'Bulldozer' architecture.

[Harshith Mohan]

It is 4 pairs of modules, in each pair one module performs one type of task and the other performs another.

 

It is better to refer to AMD FX chips as '8 thread' rather than '8 core'.

 

Have a look here to gain a better understanding.

Thanks.. So its something like hyperthreading in intel cpus?

[iNothing]

Thanks.. So its something like hyperthreading in intel cpus?

not really

 

cant go into detail, its late.

[Askew]

Thanks.. So its something like hyperthreading in intel cpus?

 

Although it may appear somewhat similar from a surface glance, the answer is no.

[Wiff]

I already had the same thought, if it realy had 8 cores it would be uncoolable hot with the stock cooler, sice the i7 4770 already needs about 125 watts, and that explains why the i7s with 6 cores are so much faster than an oc'D fx 8350

[JAKEBAB]

I already had the same thought, if it realy had 8 cores it would be uncoolable hot with the stock cooler, sice the i7 4770 already needs about 125 watts, and that explains why the i7s with 6 cores are so much faster than an oc'D fx 8350

Why would it be uncoolable? they could just turn the clocks down. also 4770 only has a tdp of 84w and the 6 cores on intel have a tdp of 130w.

[Wiff]

yes, but if the fx 8350 had 8 cores on over 3 Ghz, it would be about 160 watts, which wouldnt be very easy to handle for the stock cooler

[vitor_cut]

again?

the fx-8xxx have 4 BD/PD clusters in each cluster you have 2 fisical cores that share an FPU. that results in a lower IPC

so 4*2=8 cores in 4 compute clusters,

in intel case you have 2/4/6 fisical cores each have a dedicated FPU and 2 data "pipelines" ( in HT capable chips) to each core enabeling to treads per core that results in a higher IPC

[vm'N]

The bulldozer family are using a core technology called CMT (cluster core, essentially what AMD calls an module).

 

CMT is basically fusion two cores together, and removing the redundant parts.

 

Or you could look at it the other way around and say it is an regular core with duplicated components like integer pipelines and I/O pipelines (steamroller added additional decode pipelines).

 

 

The core share certain things like the front-end (branch predictor, fetch and decoders) and the SIMD (FPU).

 

The FX 8350 is 4 CMT cores.

 

 

again?

the fx-8xxx have 4 BD/PD clusters in each cluster you have 2 fisical cores that share an FPU. that results in a lower IPC

so 4*2=8 cores in 4 compute clusters,

in intel case you have 2/4/6 fisical cores each have a dedicated FPU and 2 data "pipelines" ( in HT capable chips) to each core enabeling to treads per core that results in a higher IPC

No, it is not 2 physical cores in the module. It is one physical module. The front end and the I/O is what is causing the bad IPC.

 

Intel cores, are fully cores, just like jaguar cores. Only CMT designs are sharing components. What exactly do you mean with "data pipelines"?

 

SMT (hyper-threading) is almost fully a software implementation, where CMT is almost a hardware implementation.

 

Example; The 4670k is an 4770k with an defective L3 cache. The 4770k doesn't have additional "data pipelines".

[vitor_cut]

The bulldozer family are using a core technology called CMT (cluster core, essentially what AMD calls an module).

 

CMT is basically fusion two cores together, and removing the redundant parts.

 

Or you could look at it the other way around and say it is an regular core with duplicated components like integer pipelines and I/O pipelines (steamroller added additional decode pipelines).

 

 

The core share certain things like the front-end (branch predictor, fetch and decoders) and the SIMD (FPU).

 

The FX 8350 is 4 CMT cores.

 

 

No, it is not 2 physical cores in the module. It is one physical module. The front end and the I/O is what is causing the bad IPC.

 

Intel cores, are fully cores, just like jaguar cores. Only CMT designs are sharing components. What exactly do you mean with "data pipelines"?

 

SMT (hyper-threading) is almost fully a software implementation, where CMT is almost a hardware implementation.

 

Example; The 4670k is an 4770k with an defective L3 cache. The 4770k doesn't have additional "data pipelines".

 

 

No. you have 2 fisical cores in each BD/PD cluster that shares a comun FPU, and that is the main reason for poor IPC in BD/PD chips

 

On INTEL side you have a dedicated FPU per core, and in HT chips you have 2 pipelines conecting the core to the FPU

 

ex: 4670K : 4 cores, 4 FPUs, 4 pipelines= 4 cores/ 4 treads

ex: 4770K: 4 cores ,4 FPUs, 8 piplelines= 4 cores/ 8 treads

[harrynowl]

8 Physical integer cores but 4 FPUs and 4 sets of L2. They have an individual pipeline though.

[vm'N]

By fisical you mean physical right?

 

Second, there are ONLY 4 CMT cores. Take a look at some die pictures. You can only spot 4 cores.

 

A core isn't just the ALU cluster, a core is much more than simply the backend.

 

It have been proven that even a single 128bit FMAC SIMD would be sufficient for most people. Piledriver have 2x128bit SIMD and 2xMMX clusters.

 

As I described earlier, the bad IPC is caused by the frontend and the I/O, and not the flexFPU as you suggested. Please do you have any evidence that the shared FPU is causing the poor IPC. It simply seems to unreasonable.

 

 

 

Also the 4770k DOES NOT have more pipelines.

[vitor_cut]

http://www.extremetech.com/computing/100583-analyzing-bulldozers-scaling-single-thread-performance

 

http://www.anandtech.com/show/868/3

[vm'N]

Can you please refer to which page they are discussing bulldozers issue? I won't read through an entire analyze.

 

Also you have to understand that most software aren't coded for floating point, so it will have little reflection of the actual IPC.

 

 

Also I cannot find anywhere in the anandtech post where he mentioned that the core I7 4770k have twice the "data pipelines".

 

You do realize that the core I5 4670k is an 4770k with a defective cache? Just like how the FX 6300 is an FX 83xx with an defective module.

[vm'N]

Okay, just because I don't want to play this game much further I will go slightly more into details.

 

SMT (hyper-threading) is in use because newer architectures have such a wide execution stage, that it is hard for a single thread to successfully utilize all the resources.

 

With SMT, you have another thread running, where both threads are sharing all the resources dynamically.

 

SMT is almost purely a software implementation, only few changed are made to the architecture itself (like improved fetch, more registers and so on).

 

 

 

To why bulldozer is getting throttled.

 

Bulldozer is sharing the frontend (branch predictor, fetch and decoders). Bulldozer is also a fairly long architecture, so already here you will need a good branch predictor. But since this is shared between both cores, there are greater risk for a prediction fail.

 

Then there is the decoders. bulldozer is running with 4 decoders (dynamically shared between both cores), so under heavy decoding, you will notice that the decoders alone is bottlenecking the entire system.

 

And not even to mention the I/O, which would take pages to address the issues (to get a detailed point of view ofcs).

 

 

So please stop this nonsense, as I feel you have a lesser knowledge on CPU architecture (you can always do some readups, anyone have to start at some point), but next time please be open for new information.

[vitor_cut]

Can you please refer to which page they are discussing bulldozers issue? I won't read through an entire analyze.

 

Also you have to understand that most software aren't coded for floating point, so it will have little reflection of the actual IPC.

 

 

Also I cannot find anywhere in the anandtech post where he mentioned that the core I7 4770k have twice the "data pipelines".

 

You do realize that the core I5 4670k is an 4770k with a defective cache? Just like how the FX 6300 is an FX 83xx with an defective module.

 

i would read the entire anlyze, and i would search for more info and other opinions, sometimes we read out of contex thing and take the wrong impression.

 

regarding the arquitecture of the CPUs i can not agree with you, there are more things to that

[XYrZbest]

I always wondered this because there are 8 core 5ghz amd CPUs that don't come close to the4960x and that is only a 6 core at 4ghz I believe

[vm'N]

Performance is more bound to architecture than clockspeed and core count.

 

The FX 9590 looks good on the cover, but as soon as you go in depth, you will notice the reasons for why it is falling behind.

[XYrZbest]

That's what I thought because spec wise the 9590 look so much better than the 4960x when it really isn't close but you can look in my sig and figure out why

[Jumper118]

it has 8 cores, they are just old and slow, because they were slow when they came out. just because they are as slow as quad cores does not mean they are quad cores.

[vm'N]

It is by fact not 8 seperate cores. This is by fact.

It is a quad core with CMT.

[harrynowl]

it has 8 cores, they are just old and slow, because they were slow when they came out. just because they are as slow as quad cores does not mean they are quad cores.

I'm pretty sure Bulldozer was designed to compete with Nehalem as that's when AMD realised K10 was pretty much EOL in terms of how it was going to scale tdp/clockspeed wise. Then they ran out of money and sold their fabs and had to delay it over and over

 

So instead in 2012 we just got a boatloads of Conroe/Penryn IPC cores

[Jumper118]

I'm pretty sure Bulldozer was designed to compete with Nehalem as that's when AMD realised K10 was pretty much EOL in terms of how it was going to scale tdp/clockspeed wise. Then they ran out of money and sold their fabs and had to delay it over and over

 

So instead in 2012 we just got a boatloads of Conroe/Penryn IPC cores

i'm pretty sure they were actually design to compete with prescott with the worst power/performance ratio ever and go down in ipc.  they did an intel.

[Faa]

It is by fact not 8 seperate cores. This is by fact.

It is a quad core with CMT.

O c'mon there's not even a definition for a core. How exactly becomes a CMT a fake x core cpu and SMT are full cores? FPU's didnt even exist back in the old days, the ALU is considered as a CPU and FPU's are processors on their own. If they can each work independetly theyre seperated thats obvious enough. The OS isn't going to recognize 8 cores if there aren't 8 ALU's. In the end it's a real 8 core - CMT doesn't make it a fake 8 core.