Are you getting Deja vu? 14900KS releases and breaks the clock speed record at 9.1GHz

[Forbidden Wafer]

22 hours ago, dizmo said:

If you're doing "real work", wouldn't you be after a Xeon anyway? 

If it has trash cores, no. In this sense, AMD threadripper or epyc are the way to go. Or an Ampere Altra, which I'm working on now.
160 cores crunching my simulations super quickly. It is like, 40x faster than the stupid laptop my job provided me originally

[dogwitch]

1 hour ago, porina said:

Not sure what you're trying to say here. If it is there are 0 PCIe lanes between CPU and chipset, that is correct and normal. Intel use their own protocol connection. You still use chipset lanes like normal.

with how little pci lanes are left. some form of bifercation is going on for the m.2 slot and chipset.

[porina]

5 minutes ago, dogwitch said:

with how little pci lanes are left. some form of bifercation is going on for the m.2 slot and chipset.

Intel chipset connection doesn't use PCIe lanes at all. They use DMI 4.0 x8 which is equivalent to PCIe 4.0 x8, and 5.0 x4. So same bandwidth available between CPU and chipset as on AM5.

 

The user available CPU PCIe lanes is a small advantage to AM5, which has 16+4+4 supporting 5.0. The remaining 4 lanes go to the chipset so are not user accessible. Intel side has 16+4, with the 16 supporting 5.0 and the 4 supporting 4.0 only. Without impacting the x16 slot, if the AM5 mobo is wired to give such (they may use some lanes for other things instead), then you could have two 5.0 SSDs connected to the CPU, vs one 4.0 SSD on Intel. In practice, on Intel side you can slap extra SSDs off chipset connection for no real world impact outside of extremely niche scenarios. Platform lanes are about the same on both. If anything I'd have more concerns about bandwidth choking with the two chipset AM5 implementations.

[dogwitch]

3 hours ago, porina said:

Intel chipset connection doesn't use PCIe lanes at all. They use DMI 4.0 x8 which is equivalent to PCIe 4.0 x8, and 5.0 x4. So same bandwidth available between CPU and chipset as on AM5.

 

The user available CPU PCIe lanes is a small advantage to AM5, which has 16+4+4 supporting 5.0. The remaining 4 lanes go to the chipset so are not user accessible. Intel side has 16+4, with the 16 supporting 5.0 and the 4 supporting 4.0 only. Without impacting the x16 slot, if the AM5 mobo is wired to give such (they may use some lanes for other things instead), then you could have two 5.0 SSDs connected to the CPU, vs one 4.0 SSD on Intel. In practice, on Intel side you can slap extra SSDs off chipset connection for no real world impact outside of extremely niche scenarios. Platform lanes are about the same on both. If anything I'd have more concerns about bandwidth choking with the two chipset AM5 implementations.

tbh why i brought it up. is wendell lvl1tech found recently.

mobo manf was bifurcating with out telling anyone.

idk if it wsa intel or amd .

 

[leadeater]

On 3/15/2024 at 7:03 AM, starsmine said:

I swear 90% of the time I see this in relation to hardware, its not what is the driving factor outside of say, price. The engineering is. These companies do not generally sandbag when ahead unless forced to by some other factor.

Oh they can and do sandbag, it's about how. It's called product segmentation. You have Intel spending a lot of engineering resources on making their uarch slightly better and slighter faster which is not sandbagging however leaving the actual consumer product portfolio in a complete state of underdevelopment due to lack of competition while on their enterprise/datacenter product portfolio actually bringing to market significant product developments not just based on uarch improvements but actual full SoC/CPU development and progression.

 

Intel was never forced to do this, there was no logical business reason to over invest and over spend in consumer desktop products with no reason to do so, so they didn't.

 

There is very little demand for performance scaling in the consumer market, small gains is actually "enough" while enterprise/datacenter actually does demand and required generation over generation significant improvements to sustain and maintain that market growth and their requirements overwise datacenter operators would actually run out of rack space, floor space, building space, land area, power deliver etc. Not only do they actually require it, truly, but will also pay for it meaning Intel delivered on product developments to suit those customer demands and requirements.

 

There is a huge difference in product development between Intel consumer and enterprise/datacenter portfolios up until consumer market competition reappeared.

 

And if you think otherwise then Intel actually halving their price of entire product stacks in workstation and server literally as soon as AMD showed real market competition, on existing products!, is very damning evidence of this. You can't half the price if it's not still actually profitable which means the margin on it before was significantly higher specifically due to lack of competition not engineering costs etc.

[williamcll]

How do you even cool 510W ?

[filpo]

2 hours ago, williamcll said:

How do you even cool 510W ?

MAGIC!

 

and 600 dollars

[Mark Kaine]

On 3/16/2024 at 7:31 AM, williamcll said:

How do you even cool 510W ?

intel stock cooler!

[jagdtigger]

This is just plain stupid. A pathetic attempt at shouting "we are still relevant, we are still the king, look at us".............

[BrandonTech.05]

Me at 9.1 GHz

[BrandonTech.05]

On 3/16/2024 at 2:31 AM, williamcll said:

How do you even cool 510W ?

I think Intel is going to have to start increasing their ihs size or just the overall size of their chips. They are constantly at the the very edge of how much heat you can physically remove from a small area. 

[starsmine]

36 minutes ago, BrandonTech.05 said:

I think Intel is going to have to start increasing their ihs size or just the overall size of their chips. They are constantly at the the very edge of how much heat you can physically remove from a small area. 

other then that being a misleading conclusion. Raptor lake is the last arch without tiles. 
Meteor lake and everything after (arrow lake) will be tile based. 

[TetraSky]

Hot damn this CPU uses a lot of power by itself. AMD being at the top of the charts for points per watt is not surprising in the least.

I for one am really hopeful that the chiplet design Intel is working on will finally bring that power usage back down. This is getting ridiculous.

[cmndr]

On 3/14/2024 at 10:09 AM, Forbidden Wafer said:

While it is cool (or actually, really hot), the E-Cores are complete garbage.

They're fine. They're reasonably performant and they don't really do any harm for most use cases while making MT use cases a fair deal more performant. 

[AnonymousGuy]

On 3/28/2024 at 8:39 AM, starsmine said:

other then that being a misleading conclusion. Raptor lake is the last arch without tiles. 
Meteor lake and everything after (arrow lake) will be tile based. 

Stacked tiles are going to be the same problem though.  It's going to be even worse on the datacenter side where the cores are in middle layers of the stack.

[GoStormPlays]

we got a 9.1 ghz processor before GTA 6, that's nice