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How do Ryzen CPUs exactly work with RAM?

I've got three questions related to this:
1- Why are Ryzen CPUs affected the most by the frequency of RAM?

2- Why is this not the case with Intel CPUs?
3- How does the infinity fabric work?

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I think this article, answers you questions pretty well

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1. Because the infinity fabric is linked to the memory speed.

2. Different architectures work differently,

3. Question for AMD engineers. The answer depends on your knowledge levels about CPU interconnects, busses and other transport protocols.

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very butchered science
1. ryzen cpu are not 100% connected, so data needs to go to ram then back to other cores
2. intel they're much more unified, single die
3. magic it's what connects the cores together

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35 minutes ago, ZeRedz said:

1- Why are Ryzen CPUs affected the most by the frequency of RAM?

2- Why is this not the case with Intel CPUs?
3- How does the infinity fabric work?

1-infinty fabric is directly affected by memory, it will run at the same speed and latency as the memory you have.

2-intel cpus dont have infinity fabric

3-it is a form of core communication, each core is able to talk to whatever core it wants, and each core can talk to the memory whenever it wants.

 

take #3 with a grain of salt, that is my understanding, but i could be completely wrong, feel free to correct me.

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#3 Infinity Fabric is the replacement name for Hyper Transport link. It is the system bus that connects peripherals, NB, multi-socket Cpus ect. 

 

The reason why we see performance increase unlike with HT, IF is saturated enough that increasing the bandwidth with overclocking it yields better performance results. However it's intended to Run at 1066mhz and does not have to be linked to memory frequency. 

 

Since I haven't read much about overclocking the Infinity Fabric on it's own and measuring performance gains, I haven't much to comment about it other than in the past, Solely overclocking the Hyper Transport brought very small gains in performance to the table. But it does look that AMD was able to better utilize the bandwidth available.

 

 

 

 

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2 hours ago, ZeRedz said:

1- Why are Ryzen CPUs affected the most by the frequency of RAM?

Because zen as an architecture is built using multiple ccxs (ccx is basically the container of the cores ) and those house cache with in them obviously and because there is multiple ccxs if they want to communicate with each other to send information it takes time since there is multiple ccxs data has to basically go through so the higher the frequency of ram the faster it can be read and written to by these cores that are spread in multiple ccxs

 

2 hours ago, ZeRedz said:

2- Why is this not the case with Intel CPUs?

Latency still exists in Intel cpu's it's just not as noticable since it has a better imc so ocing ram is a breeze and since there is only one ccx so the "data" has to go to one ccx which indeed does take time and latency but not as much as the multiple ccxs that are apparent on AMD cpu's

2 hours ago, ZeRedz said:

3- How does the infinity fabric work?

It's basically a 12nm interconnect that connects all the ccxs so they can basically work together 

 

I'm sure someone has a better way to explain this but hope this helps :D

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14 hours ago, TofuHaroto said:

Because zen as an architecture is built using multiple ccxs (ccx is basically the container of the cores ) and those house cache with in them obviously and because there is multiple ccxs if they want to communicate with each other to send information it takes time since there is multiple ccxs data has to basically go through so the higher the frequency of ram the faster it can be read and written to by these cores that are spread in multiple ccxs

 

Latency still exists in Intel cpu's it's just not as noticable since it has a better imc so ocing ram is a breeze and since there is only one ccx so the "data" has to go to one ccx which indeed does take time and latency but not as much as the multiple ccxs that are apparent on AMD cpu's

It's basically a 12nm interconnect that connects all the ccxs so they can basically work together 

 

I'm sure someone has a better way to explain this but hope this helps :D

Regarding the first answer, what you're basically is saying that if there's an instruction in one of the CCXs that it has to execute, it has to go through every single CCX to find that instruction and the speed at which it goes through the CCXs is dependent on the RAM frequency?

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8 hours ago, ZeRedz said:

Regarding the first answer, what you're basically is saying that if there's an instruction in one of the CCXs that it has to execute, it has to go through every single CCX to find that instruction and the speed at which it goes through the CCXs is dependent on the RAM frequency?

Not necessarily that 

It's a very rare occurrence that a task is  executed only in one ccx 

Because one ccx might have 2 really efficient binned cores and 2 really bad ones for example and the other might have the 2 other efficient cores 

So if the cpu said , hey I have these efficient cores in ccx 1 and I have these other efficient cores in ccx 2 then executing the task using the binned cores in both ccxs will be faster so the data or the instructions have to go through the ccxs using the interconnect 

Now because the interconnect has to work 

It's speed is based on the frequency of your ram that's why it matter 

Everything kind of connects with each other 

The ccxs work with each other faster if the interconnect is faster the interconnect works faster if the ram is faster 

 

Sorry if this is a janky explanation I kind of just woke up lmao :D

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1 minute ago, pstarlord said:

 

 

 

^ or you can watch a video ;)

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9 hours ago, TofuHaroto said:

Not necessarily that 

It's a very rare occurrence that a task is  executed only in one ccx 

Because one ccx might have 2 really efficient binned cores and 2 really bad ones for example and the other might have the 2 other efficient cores 

So if the cpu said , hey I have these efficient cores in ccx 1 and I have these other efficient cores in ccx 2 then executing the task using the binned cores in both ccxs will be faster so the data or the instructions have to go through the ccxs using the interconnect 

Now because the interconnect has to work 

It's speed is based on the frequency of your ram that's why it matter 

Everything kind of connects with each other 

The ccxs work with each other faster if the interconnect is faster the interconnect works faster if the ram is faster 

 

Sorry if this is a janky explanation I kind of just woke up lmao :D

So, just to sum it up, it's faster for an instruction to be executed using efficient cores in both CCXs than to be executed in one CCX with two efficient ones and two somewhat less efficient ones? And the interconnect to which you're referring to is the infinity fabric? 

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1 minute ago, ZeRedz said:

So, just to sum it up, it's faster for an instruction to be executed using efficient cores in both CCXs than to be executed in one CCX with two efficient ones and two somewhat less efficient ones? And the interconnect to which you're referring to is the infinity fabric? 

Pretty much the 2 efficient cores is just an example it can be 1 or even 4 or even 3 depending on the ccx layout and the core count 

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Just now, TofuHaroto said:

Pretty much the 2 efficient cores is just an example it can be 1 or even 4 or even 3 depending on the ccx layout and the core count 

Right. I got to ask, why does a CCX tend to have a core or two that are somewhat inefficient in comparison to the other efficient cores?

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2 minutes ago, ZeRedz said:

Right. I got to ask, why does a CCX tend to have a core or two that are somewhat inefficient in comparison to the other efficient cores?

To the other less efficient cores I'm gonna assume ? 

Because silicon is inconsistent in quality 

You might get a core that is binned with great silicon and the other with crappy silicon

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7 minutes ago, TofuHaroto said:

To the other less efficient cores I'm gonna assume ? 

Because silicon is inconsistent in quality 

You might get a core that is binned with great silicon and the other with crappy silicon

Alright! Thanks for the explanation!

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6 minutes ago, ZeRedz said:

Alright! Thanks for the explanation!

Any time :D

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