AMD Readies 16-core Processors with Full Uncore

[TOMPPIX]

AMD released developer documentation for a new processor it's working on, and the way it's worded describes a chip with 8 modules, working out to 16 cores, on a single piece of silicon, referred to as Family 15h Models 30h - 3fh. This is not to be confused with the company's Opteron 6300-series "Abu Dhabi" chips, which are multi-chip modules of two 8-core dies, in the G34 package. 

 

 

What's more, unlike the current "Abu Dhabi" and "Seoul" chips, the new silicon features a full-fledged uncore, complete with a PCI-Express gen 3.0 root complex that's integrated into the processor die. In what's more proof that it's a single die with 8 modules and not an MCM of two dies with 4 modules each, the document describes the die as featuring four HyperTransport links; letting it pair with four other processors in 4P multi-socket configurations. Such systems would feature a total core count of 64. There's no clarity on which exact micro-architecture the CPU modules are based on. Without doubt, AMD is designing this chip for its Opteron enterprise product stack, but it should also give us a glimmer of hope that AMD could continue to serve up high-performance client CPU, only ones that can't be based on socket AM3+.

 

SOURCE

[Nineshadow]

8 modules...2 cores per module.

Not again...

[Kilerbomb]

Some guy on the comments of the article:

 

enjoy the 50000W TDP.

 

 

[SkilledRebuilds]

8 modules...2 cores per module.

Not again...

Thats not the actual problem..

 

Needs more floating point units as many as integer.... 1:1 not 1:2

[That Norwegian Guy]

AMD: Burning the heretical caches and FPUs at the cross since 1371.

[Hazorazor]

Possibly the Piledriver based Warsaw CPU?

[Guest GRRigger]

Thats not the actual problem..

 

Needs more floating point units as many as integer.... 1:1 not 1:2

not really. the difference in performance would be there, yes, but only 5 - 20 %

http://www.extremetech.com/computing/138394-amds-fx-8350-analyzed-does-piledriver-deliver-where-bulldozer-fell-short/2

 

alot of it is shared stuff, but it can still work on 2 thread simontaniously, and 2 128bit or 1 256 bit fp

 

http://www.reddit.com/r/buildapc/comments/1e8226/

[ZetZet]

not coming to consumers any time soon, imo.

[Kamina]

Funny how I posted this yesterday. 

<3

[brownninja97]

This will either be decent or all hell will break lose and it will burn down the world.

[isteelsolz]

AMD's Roadmap shows they have no intention to change the architecture from the piledriver based Vishera FX cpu's, but that does not mean they wont update the platform. My best guess at was this news means is that they will release a new processor based on the AM4 (AM3++? idk) socket, with an updated (1090FX?) chipset with 8 modules and 16 cores, but still keep the same old architecture. Unlikley but lets be hopeful. This is a departure from the roadmap, but they have lied to us in the past about product updates. "No new GPU's in 2013" then the 290X happened. Heres to vishera 2.0

 

[Humbug]

Big new operton server chips are always a good sign.

Because historically any high end desktop chips will be cut down versions of these CPUs.

[TechFan@ic]

This is legit 16 core Steamroller CPUs exist, page 30.
PDF Document
 

2.1 Key Microarchitecture Features
AMD Family 15h processors include many features designed to improve software performance. The
internal design, or microarchitecture, of these processors provides the following key features:
• Up to 8 Compute Units (CUs) with 2 cores per CU
• Integrated DDR3 memory controller (two in some models) with memory prefetcher
• 64-Kbyte L1 instruction cache per CU (96-Kbyte for models 30h–4Fh) this is a clear indicator that family 30H-4Fh are in fact Steamroller based because Piledriver only has a 64bit L1 instruction cache.
• 16-Kbyte L1 data cache per core
• Unified L2 cache shared between cores of CU
• Shared L3 cache on chip (for supported platforms) except for models 10h–1Fh
• 32-byte instruction fetch
• Instruction predecode and branch prediction during cache-line fills
• Decoupled prediction and instruction fetch pipelines
• Updated instruction decoding (See section 2.3 on page 31.)
• Dynamic scheduling and speculative execution
• Two-way integer execution
• Two-way address generation
• Two-way 128-bit wide floating-point and packed integer execution
• Legacy single-instruction multiple-data (SIMD) instruction extensions, as well as support for
XOP, FMA4, VPERMILx, and Advanced Vector Extensions (AVX).
• Support for FMA, F16C, BMI and TBM instruction sets (models 10h–1Fh, 2h, and 30h–4Fh)
• Superforwarding
• Prefetch into L2 or L1 data cache
• Increased L1 DTLB size to 64 (See Section 2.9.2 on page 37.)
• Deep out-of-order integer and floating-point execution
• HyperTransport™ technology