32 Bit CPUs & PAE, >4 GB of ram?

[Jack.EXE]

I decided to make a thread explaining how the bit width effects RAM limitations, and while I did my research, I found out we've been lied to.
 
32 Bit systems can access more than 4 GB of ram.
 
Interested? follow me while I take you on a tour.

 

the formula for calculating the amount of memory a processor can access is:

Where x is the bit width of the processor's memory address.
 
this gives us:
 
8 bit CPUs can access 256 bits of ram,
16 bit CPUs can access 65,536 bits of ram, or ~64 KiB
the x86 architecture can access 4,294,967,296, or ~4GiB
the AMD64 architecture contains a 48 bit physical address, with a 16 bit virtual, allowing for 281,474,976,710,656 bits, or ~256 TiB

 

Now, as you may or may not know, you can segment ram, starting with 16 bit CPUs, allowing for multiples of 64 KiB (in 16 bit CPUs) memory sizes (ex the Commodore 128)

 

This is called PAE, and the only limit comes from the number of address pins.

 

the formula for PAE addresses is as follows:

where x is the bit width of the memory address, and y is the number of address pins above the bit width

 

example:

16 bits, 20 address pins = 1,048,576 registers, or 1 MiB

 

In supported OSes, the Pentium 4 can use PAE and it's 36 address pins to access up to 64 GiB of ram!

 

Pretty snazzy, eh?

 

Suppose we were to use PAE in an AMD64 CPU (48 bit register, 16 bit virtual, 64 address pins), we could access up to 16,777,216 TiB of ram!

 

Now, guess which OSes support PAE? Yep, Linux derivatives (and enterprise windows variants)

 

 

I just thought this was a cool tidbit of information, and I hope you find it cool as well.

2^x-1(0 being starting point)

(2^x-1) * 2^y

[Jack.EXE]

Too bad we dont have enough physical memory to take advantage of all this address space.

[antoainb]

Too bad we dont have enough physical memory to take advantage of all this address space.

 

You'd need memory sticks with aprox. 700000TiB to take advantage of that address space with a 24 DIMM slot motherboard.

 

Great post!

[Jack.EXE]

By setting bit 5(PAE) of the system register CR4 causes major changes to the page table. By default, the size of each page remains as 4 KB. Each entry in the page table and page directory becomes 64 bit long, instead of 32 bits, to allow for additional address bits. The Size of the tables do not change, however, resulting in only 512 entries per table. To solve this, an extra level of hierarchy has been added, so that CR3 now points to Page Directory Pointer Table, a short table containing four pointers, each to their own page table..

 

 

Just a bit more info, in case you were wondering how the nitty gritty of PAE works.

[Legitsu]

god  not another PAE thread PAE IS DEAD quit talking about it its fking usless anyway

[harrynowl]

god  not another PAE thread PAE IS DEAD quit talking about it its fking usless anyway

get over it this thread was dead ages ago.

[Jack.EXE]

god  not another PAE thread PAE IS DEAD quit talking about it its fking usless anyway

 

Considering this thread dates back to April 29th, i don't think you have an argument.

 

I only just found this thread recently and decided to add some information.