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I have two question and it would help me if you had some answers...

 

what is the biggest area for a cpu or gpu die (no xeon phil), is it the nehalem eight core processor (684mm sq) ?

 

what is the max bandwidth of 4 gddr5 x32 8Gb/s chip that ar in parrallel ? (64, 128, 256, 512 or 1024 Go/s)

 

thank you very much I appreciate !

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2 minutes ago, Royaleagle said:

I have two question and it would help me if you had some answers...

 

what is the biggest area for a cpu or gpu die (no xeon phil), is it the nehalem eight core processor (684mm sq) ?

 

what is the max bandwidth of 4 gddr5 x32 8Gb/s chip that ar in parrallel ? (64, 128, 256, 512 or 1024 Go/s)

 

thank you very much I appreciate !

There is a dedicated thread for CPU's on this forum.

Please do not post these sorts of questions here.

Roses are red

My name is Roy

We caught the alligator that ate the De Luca boy

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6 minutes ago, Royaleagle said:

how do I move it ?

report your own post and say that you want it moved to cpus :) but i don't think there is a real need for it to be moved

oh wait i thought you put it in gpus, nvm, do report your post and ask for it to be moved

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biggest cpu die seems to be that 8 core nehalem chip you mentioned ( frankly 684mm² is HUGE ). the biggest gpu die ever made is gp100 , used in the tesla p100 ( not yet out yet , but demo'ed by nvidia about a month or two ago ). The problem is the yield to die size ratio isn't proportional. Many factors affect yield , including process maturity etc , but generally , the yields decrease exponentially the bigger you make the chip .

The formula to calculate gddr5 bandwidth is [effective memory clock] * [bus width] /8 *2= [bandwith in MB/s ]. In this case , that would be 8000*128 ( because 4*32 = 128) /8*2 = 256GB/s.

 

 

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1 hour ago, Coaxialgamer said:

biggest cpu die seems to be that 8 core nehalem chip you mentioned ( frankly 684mm² is HUGE ). the biggest gpu die ever made is gp100 , used in the tesla p100 ( not yet out yet , but demo'ed by nvidia about a month or two ago ). The problem is the yield to die size ratio isn't proportional. Many factors affect yield , including process maturity etc , but generally , the yields decrease exponentially the bigger you make the chip .

The formula to calculate gddr5 bandwidth is [effective memory clock] * [bus width] /8 *2= [bandwith in MB/s ]. In this case , that would be 8000*128 ( because 4*32 = 128) /8*2 = 256GB/s.

 

 

thank you very much :) it is for a contest

it is enormous yeah ^^ I learn new things every day !

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Depends on the process and its maturity. Typically 500mm^2 has been the usual limit most companies were willing to push to but the lithography can potentially allow larger chips given some designing around the bigger die. I didn't know they had got up to 684mm^2, you rarely see anything go above 500mm^2 for purely economic reasons.

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