Samsung Will Begin Manufacturing AMD's 14nm Zen Core By Year's End

[patrickjp93]

For that time it were.

Itanium is functional. Hence why it is still around. It however is simply not the replacement for x86 as Intel orginally thought.

IPC is an incredible stupid measurement for performance. It however provide an idea of the effeciency of an architecture, but do not describe the performance of an architecture.

Because what about frequency, code optimization, dataraces, misprediction, cache miss, and much much more.

Also x86 takes "macro" instructions, also known as a complex instruction. This complex instruction will then be translated into AMDs/Intels own RISC-a-like code.

A single complex instruction can be translated into multipe RISC-a-like instructions.

There was never going to be a replacement of x86.

Still the days when it was easy.

No, it's not stupid, because there's a limit on the number of micro instructions one macro instruction translates to, hence why Intel can definitely say that floating point mil/dvi takes 3 cycles on Broadwell vs. Haswell's 5. Data races are a non-issue except in multi-threaded applications where we have locks and semafors which halt execution anyway. Cache misses only affect transactional processes these days and only in big-data applications. Branch misses in Intel's case lose you 1 cycle. Boo hoo.

[PortentousLad]

Isn't intel doing 10nm now? why is AMD bothering with 14? why not try and leap frog intel and do like, 8nm or something?

8? why bother with the nm scale at all make 'em out of thin air.

No seriously they probably have their reasons, I guess one could be that AMD hasn't even worked on 20nm(do they have 20nm stuff?) afaIk so they're leapfrogging that already.

[vm'N]

There was never going to be a replacement of x86.

Still the days when it was easy.

No, it's not stupid, because there's a limit on the number of micro instructions one macro instruction translates to, hence why Intel can definitely say that floating point mil/dvi takes 3 cycles on Broadwell vs. Haswell's 5. Data races are a non-issue except in multi-threaded applications where we have locks and semafors which halt execution anyway. Cache misses only affect transactional processes these days and only in big-data applications. Branch misses in Intel's case lose you 1 cycle. Boo hoo.

My fault, didn't mean that Itanium would completely replace x86. However it were to replace certain areas of x86.

Easy? Easy how? Today they already have ton of research on how to increase performance. People are been educated to deal with these things. It is easier than never.

It is still stupid. IPC alone still gives no idea of the total performance of a processor. We still need more specifications.

Multi-threading is been used more and more, data races will still be an issue. Halting executing does also hinder the processor from performing 100%.

Cache-miss can be devastating to performance, however you are correct. It is only a greater issue to big-data application.

[patrickjp93]

My fault, didn't mean that Itanium would completely replace x86. However it were to replace certain areas of x86.

Easy? Easy how? Today they already have ton of research on how to increase performance. People are been educated to deal with these things. It is easier than never.

It is still stupid. IPC alone still gives no idea of the total performance of a processor. We still need more specifications.

Multi-threading is been used more and more, data races will still be an issue. Halting executing does also hinder the processor from performing 100%.

Cache-miss can be devastating to performance, however you are correct. It is only a greater issue to big-data application.

Easier than ever?! Pal, go study quantum mechanics and nanocircuitry. It's harder than ever. We're at the scale where the flow between two parallel circuit lines can interfere with each other by magnetic induction, not to mention guaranteeing the electron is actually in the wire.

The data race is entirely a programmer-side problem. No two ways about it. And a smart lock goes to do independent tasks while threads are waiting on one another.

We need no more specifications than the x86 instruction set which a processor supports and the cycle time of those instructions. From that you can extrapolate performance easily. The rest is up to the compiler. At the time of execution the processor just has to figure out how to balance between the various running processes and arrange for fewest no-ops.

[LukeTim]

Huh?

I thought AMD had their own Fabs... Guess I was wrong?

[vm'N]

Easier than ever?! Pal, go study quantum mechanics and nanocircuitry. It's harder than ever. We're at the scale where the flow between two parallel circuit lines can interfere with each other by magnetic induction, not to mention guaranteeing the electron is actually in the wire.

The data race is entirely a programmer-side problem. No two ways about it. And a smart lock goes to do independent tasks while threads are waiting on one another.

What would be easiest? Have a lot of uneducated (compared to today) people designed processors without the greater knowlegde and experience we have today or the expert team that are currently working for the big contenders.

It is not the point if him making something that would look obsolete today, but the fact that he brought new ideas to the industry.

Data-races are a problem with multi-threading code with a serial implementation.

We need no more specifications than the x86 instruction set which a processor supports and the cycle time of those instructions. From that you can extrapolate performance easily. The rest is up to the compiler. At the time of execution the processor just has to figure out how to balance between the various running processes and arrange for fewest no-ops.

No. You even overlooked frequency. Normally you would say IPC * frequency = core performance (very simply and should not be used).

Again, IPC will only provide an idea of the effeciency of an architecture, not the overall performance.

So you are saying that the processor alone is only working with OoO, meanwhile the compiler handles everything else?

[vm'N]

Huh?

I thought AMD had their own Fabs... Guess I was wrong?

AMD have been fabless for some time now.

[LukeTim]

AMD have been fabless for some time now.

 

Just goes to show how out of the loop I am!

I haven't been all that interested in the desktop CPU game since about 2007/8 when I built my first PC.

[Mister Snow]

The thing about Jim Keller's success is that he is very good at predicting what the market will need in near future and building it. The new architecture does not need to be something revolutionary, just something that is useful today. AMD did try to go for highly multithreaded CPU whit their bulldozer arch so they sacrificed some single threaded performance but the market was not ready to go there yet which was the thing they overlooked.

[patrickjp93]

What would be easiest? Have a lot of uneducated (compared to today) people designed processors without the greater knowlegde and experience we have today or the expert team that are currently working for the big contenders.

Data-races are a problem with multi-threading code with a serial implementation.

No. You even overlooked frequency. Normally you would say IPC * frequency = core performance (very simply and should not be used).

Again, IPC will only provide an idea of the effeciency of an architecture, not the overall performance.

So you are saying that the processor alone is only working with OoO, meanwhile the compiler handles everything else?

Being an experienced person doesn't make it easier you twit! Either you understand quantum mechanics on that scale, or you don't. The rest of it is all recycled from past architectures. It is not easier today than it was in 06. It's much harder.

Frequency goes without saying! Are you really so conceited? All you need is frequency, core count, ipc for the instructions, and the instruction set. It's a simple formula whether it's RISC or CISC.

Data race is a problem in serial computing?! Omg now I know you're full of shit.

Yes, the compiler says what instructions should be executed and in what order, and OOP balances multiple processes running simultaneously so that none of them hang, and performance is maximized in all of them.

[vm'N]

Being an experienced person doesn't make it easier you twit!

It actually does. It makes it easier for the experienced team.

This is human nature. Things become easier the more we get used to it.

 

Either you understand quantum mechanics on that scale, or you don't. The rest of it is all recycled from past architectures. It is not easier today than it was in 06. It's much harder.

It is much harder for those who are not in the industry working with it.

 

Frequency goes without saying! Are you really so conceited? All you need is frequency, core count, ipc for the instructions, and the instruction set. It's a simple formula whether it's RISC or CISC.

You do realize that you can optimize the architecture for either high frequency or high IPC.

A high IPC alone tells nothing about performance, as I have repeated a ton of times.

Frequency does NOT go without saying. Piledrivers IPC is considered low, however are been equalized with the frequency and number of "cores".

That formula will have a high error-rate with advanced software.

What about CPI?

 

Data race is a problem in serial computing?! Omg now I know you're full of shit.

Please read the entire statement please.

Data-races are a problem with multi-threading code with a serial implementation.

Multi-threading != parallel implementation

[GeathX]

im talking CPU performance. if the boards were shit, thats a different question... i still know a ton of people running phenom2s OCd no problem. youre just picking on the bad things of AMDs and not looking at what intel did crappy then (granted i cant remember atm, since its too late, but i know they had their fair share of problems). when threads like these arise, you are such an intel fanboy...

 

1090t still running along fine here WOOOO and upgraded to it from a q6600

[Strator]

I don't want to get ahead of the curve here, but super excited about this. AMD have the pieces they need now to put together a winner. They will be on a competitive node, and hopefully Jim will have the arch to match. I know he has been doing mobile SoC for the last few years but these days CPU's are verging on SoC anyway (I\O, memory, Northbridge and even voltage regulation with Haswell all on the die). Lets not forget that Intel's Core arch, which got them off the GHz and heat path of Netburst, was based on their mobile Pentium M. Not that SoC from a phone will directly scale to laptop or desktop chips, but at least they have some one who knows, and cares, about efficency.

 

Just my two cents, we can dream can't we.

[patrickjp93]

It actually does. It makes it easier for the experienced team.

This is human nature. Things become easier the more we get used to it.

 

It is much harder for those who are not in the industry working with it.

 

You do realize that you can optimize the architecture for either high frequency or high IPC.

A high IPC alone tells nothing about performance, as I have repeated a ton of times.

Frequency does NOT go without saying. Piledrivers IPC is considered low, however are been equalized with the frequency and number of "cores".

That formula will have a high error-rate with advanced software.

What about CPI?

 

Please read the entire statement please.

Multi-threading != parallel implementation

The game changes with every node shrink. New parts of physics stop having negligible effects and start having catastrophic ones. It doesn't get any easier to shrink from node to node. get that through your thick skull! The overall templating is easier, but to actually implement it gets harder and harder at an exponential rate.

 

You can optimize for both.

 

Frequency goes without saying. You obviously need a clock telling you how often a CPU can do something. that's barebones common sense. 

 

CPI is little more than an aggregate of this. Certain jobs get done in a certain amount of time which is a simple formula of how many instructions, which ones, in which order, and how many clock cycles per instruction. Done. It's a result of other basic optimizations.

 

Multithreading is exactly = to parallel implementation. You have instruction-level parallelism (what can various instructions in the pipeline be doing so they don't interfere with each other), data-level parallelism (the important one), and thread-level parallelism (separating jobs into distinct lines of execution, which is mainly pointless in a superscalar architecture. It's only useful at the programming level for easy separation of code blocks).

 

There is no such thing as a data race condition in serial computing because each result is laterally dependent on the previous results, not sideways dependent on a separate line of execution. Seriously who taught you programming and computer engineering?

[vm'N]

The game changes with every node shrink. New parts of physics stop having negligible effects and start having catastrophic ones. It doesn't get any easier to shrink from node to node. get that through your thick skull!

I'm not saying it is not more advanced and technical today than it was in the past.

However we constantly move forward, reusing technology, theories and information from the past.

We keep advancing on the same technologies, and that is doomed to scale bad in the long run.

Inventing is as hard as advancing.

Just to be clear: I'm not saying that the technology today isn't 100 times more advanced than in the past.

The overall templating is easier, but to actually implement it gets harder and harder at an exponential rate.

 

This is true.

You can optimize for both.

Yes, and engineers does. However you will need to find a balance between.

Increasing one will degrease the other. Heat is a big issue with this.

Frequency goes without saying. You obviously need a clock telling you how often a CPU can do something. that's barebones common sense.

No. Because you cannot determine a processors throughput only based on IPC, as it requires more factors.

This is my point. IPC alone cannot be a measurement for performance.

CPI is little more than an aggregate of this. Certain jobs get done in a certain amount of time which is a simple formula of how many instructions, which ones, in which order, and how many clock cycles per instruction. Done. It's a result of other basic optimizations.

CPI is also very depended on the architecture. Like have many stages the architecture have.

Architectures optimized for high frequency normally have a very long pipeline, which increase the CPI.

Haswell have a "short" pipeline, and therefore have a lower CPI.

Multithreading is exactly = to parallel implementation. You have instruction-level parallelism (what can various instructions in the pipeline be doing so they don't interfere with each other), data-level parallelism (the important one), and thread-level parallelism (separating jobs into distinct lines of execution, which is mainly pointless in a superscalar architecture. It's only useful at the programming level for easy separation of code blocks).

Multi-threading does not equal a parallel implementation.

An example would be having multiple workers work on the same ressourcepool.

This would be considered a serial implementation.

This is where data-races will occur.

A parallel implementation of the code, would instead have multiple ressourcepools (each worker gets its own), and it will work complete parallel.

However not all workloads can be done this way. Great example is games (which is also multithreading of a serial implementation).

There is no such thing as a data race condition in serial computing because each result is laterally dependent on the previous results, not sideways dependent on a separate line of execution. Seriously who taught you programming and computer engineering?

Please re-read my comment.

Data-races are a problem with multi-threading code with a serial implementation.

[Brainless906]

Nah, I'll put my dad's Q6600 up against any of AMD's chips at the time.

 

 

orly.....lets also remember the phenoms were beast mode OCs.

 

My brother has my old 1055t and its still running strong @ 3.4ghz on air.

 

The 1055t was released in 2010 vs the q6600 in 2007 but your the one who commented trying to downplay the newer processor.

 

To be fair lets put it up against something released in the same time period like the x4 9850...oh...it still got stopped even before the phenoms silly OC-ability....

also your q6600 was released at over $800USD while the 9530 was just a little over 200....

 

Hi my names patrickjp93, im not a fanboy i swear, i'll just downplay absolutely everything AMD has ever done.

 

[patrickjp93]

orly.....lets also remember the phenoms were beast mode OCs.

 

My brother has my old 1055t and its still running strong @ 3.4ghz on air.

 

The 1055t was released in 2010 vs the q6600 in 2007 but your the one who commented trying to downplay the newer processor.

 

To be fair lets put it up against something released in the same time period like the x4 9850...oh...it still got stopped even before the phenoms silly OC-ability....

also your q6600 was released at over $800USD while the 9530 was just a little over 200....

 

Hi my names patrickjp93, im not a fanboy i swear, i'll just downplay absolutely everything AMD has ever done.

 

The X4 9850 does not beat the Q6600 in any test unless it's a golden chip in the first place. Next cherry-picked benchmark/test?

 

AMD used to be good, and then to make up for their lack in ability they bought ATI at more than 1.5x the price they should have. Keller is good, but he's been out of the big chip game for a long time. I maintain healthy skepticism until Zen is released and thoroughly tested.

[patrickjp93]

I'm not saying it is not more advanced and technical today than it was in the past.

However we constantly move forward, reusing technology, theories and information from the past.

We keep advancing on the same technologies, and that is doomed to scale bad in the long run.

Inventing is as hard as advancing.

Just to be clear: I'm not saying that the technology today isn't 100 times more advanced than in the past.

 

This is true.

Yes, and engineers does. However you will need to find a balance between.

Increasing one will degrease the other. Heat is a big issue with this.

No. Because you cannot determine a processors throughput only based on IPC, as it requires more factors.

This is my point. IPC alone cannot be a measurement for performance.

CPI is also very depended on the architecture. Like have many stages the architecture have.

Architectures optimized for high frequency normally have a very long pipeline, which increase the CPI.

Haswell have a "short" pipeline, and therefore have a lower CPI.

Multi-threading does not equal a parallel implementation.

An example would be having multiple workers work on the same ressourcepool.

This would be considered a serial implementation.

This is where data-races will occur.

A parallel implementation of the code, would instead have multiple ressourcepools (each worker gets its own), and it will work complete parallel.

However not all workloads can be done this way. Great example is games (which is also multithreading of a serial implementation).

Please re-read my comment.

Except haswell has a bigger CPI than Westmere. Also, no, frequency scaling does not decrease ipc inherently. The only time this occurs is when the clock rate is moving beyond the speed at which electricity can flow through the path of an instruction, causing an overlap/miss. You can have perfect IPC and high frequency.

 

You're going in circles. IPC and the instruction set are all you need to gauge how effective a CPU will be clock for clock. Multiply by clocks and you get total throughput obviously, but this is very basic logic any halfwit should understand.

 

Multiple workers on the same data set is instruction-level parallelism and falls right in line with what I said above. There is no data race condition if you build it correctly.

[Faa]

What? IPC in itself explain nothing about the performance of a processor. IPC is a stupid messurement.

I wonder how IPC meassure the difference between integer and float calculations, between predictable and non-predictable code, between loops and whatnot.

Have you seen anyone saying AMD can do 2 instructions a cycle and Intel 4 instructions a cycle? Patrick would be an exception. You're refering to clock-for-clock performance with IPC and you damn hell know this.

[Brainless906]

The X4 9850 does not beat the Q6600 in any test unless it's a golden chip in the first place. Next cherry-picked benchmark/test?

 

AMD used to be good, and then to make up for their lack in ability they bought ATI at more than 1.5x the price they should have. Keller is good, but he's been out of the big chip game for a long time. I maintain healthy skepticism until Zen is released and thoroughly tested.

http://www.legionhardware.com/articles_pages/intel_core_2_quad_q6600_vs_amd_phenom_x4_9850,6.html

http://www.techspot.com/review/93-amd-phenom-9850-black-edition/

http://hothardware.com/Reviews/AMD-Phenom-X4-9850-B3-Revision/?page=1

http://www.guru3d.com/articles_pages/amd_phenom_x4_9850_black_edition_review,7.html

 

850ish bucks vs 235ish bucks this isnt even a competition. Even if it was 10-15 percent slower the extreme cost is...well...extreme...(oh wait they dropped the q6600 to 500ish bucks that April...WHAT A STEAL!)

 

 

omg golden chips errrwhere! Ananananananandtech not to be trusted!

You're not skeptical you're down right certain they are going to fail. 

 

#intel/nvidiamasterrace

[LukaP]

http://www.legionhardware.com/articles_pages/intel_core_2_quad_q6600_vs_amd_phenom_x4_9850,6.html

http://www.techspot.com/review/93-amd-phenom-9850-black-edition/

http://hothardware.com/Reviews/AMD-Phenom-X4-9850-B3-Revision/?page=1

http://www.guru3d.com/articles_pages/amd_phenom_x4_9850_black_edition_review,7.html

 

850ish bucks vs 235ish bucks this isnt even a competition. Even if it was 10-15 percent slower the extreme cost is...well...extreme...(oh wait they dropped the q6600 to 500ish bucks that April...WHAT A STEAL!)

 

 

omg golden chips errrwhere! Ananananananandtech not to be trusted!

You're not skeptical you're down right certain they are going to fail. 

 

#intel/nvidiamasterrace

dont bother with him, he is so deep in the fanboy he doesnt even accept nvidia also, he claims that AMD and NV wont improve their chips in 2 years and intel iGPUs will have dominance over the midrange sector. you can see how non fanboy that is... /sarcasm

 

(and this was written by someone who by choice (mostly irrational) would never use AMD, and would consider himself an intel/NV fanboy at heart)

[Brainless906]

dont bother with him, he is so deep in the fanboy he doesnt even accept nvidia also, he claims that AMD and NV wont improve their chips in 2 years and intel iGPUs will have dominance over the midrange sector. you can see how non fanboy that is... /sarcasm

 

(and this was written by someone who by choice (mostly irrational) would never use AMD, and would consider himself an intel/NV fanboy at heart)

 

 

I feel like its a bad thing but a small part of me wants the Zen chips to absolutely without question demolish everything that intel can put out, just to see how he inevitably defends his holy savior intel.

 

most of me just wants competition and even a back and for very comparative chip will make me happy but dear lord would it make me laugh to see intel fanboyism that grown due to amds lack of high end competition try to defend intel getting squashed. 

 

To bad it wont happen, pat said so

[Physc]

go #teamamd

 

no seriously, will be interesting if they can bring the performance on par with Haswell(22nm)/Broadwell(14nm)

 

nonetheless, if this goes well then I guess AMD will team up with Samsung fabs from then on? 

[LukaP]

I feel like its a bad thing but a small part of me wants the Zen chips to absolutely without question demolish everything that intel can put out, just to see how he inevitably defends his holy savior intel.

 

most of me just wants competition and even a back and for very comparative chip will make me happy but dear lord would it make me laugh to see intel fanboyism that grown due to amds lack of high end competition try to defend intel getting squashed. 

 

To bad it wont happen, pat said so

well i dont see them smashing intel, but i can see them coming up to intels league again. i mean apparently they are doing an SMT design. on 14nm. just from that, they should achieve a similar performance as intel. so i hope this makes intel do something and play an ace they have hidden...

[Brainless906]

well i dont see them smashing intel, but i can see them coming up to intels league again. i mean apparently they are doing an SMT design. on 14nm. just from that, they should achieve a similar performance as intel. so i hope this makes intel do something and play an ace they have hidden...

 

 

Yah, i like i said i'd be happy even with a competitive chip but a man can dream.....