More Ryzen 3000 info - 4.5GHZ boost & +10-15% IPC

[Stefan Payne]

8 hours ago, leadeater said:

Yea that would be nice, not sure if there is any specific reasons why keeping it to 4 is best or preferred or increasing that a to be coming thing. Maybe it has something to do with that the L3 cache is in 2MB slices per core and connecting them up gets much harder beyond 4 i.e. full mesh connection point count.

Yeah, we have to wait and see if they move from 4 Core CCX to 8 Core.

I still hope for 8 Core because it makes a bit more sense.

But yeah, having more than 4 Cores drastically increases complexity.

They might or might not have increased it.

Quote

So basically the chiplet should be the 2 CCXs, the SDF and the GMI interfaces. The GMI interfaces will connect to the I/O die SDF (or equivalent). 

Hm, if we have only one CCX per Die, Wouldn't that make the SDF thing on the CPU Die unnecessary and remove a bit other stuff as well so that you only have CPU + GMI?

You don't have anything else that needs soe switch/crossbar thingy...

 

Quote

Direct connections between chiplets I'd classify as unlikely as then you'd be back to non-uniform memory access (NUMA) again. You don't really want 'close' and 'far' cores otherwise you're in compiler optimization hell that people might not do, the hell part of it. I don't know, anything is possible.

With the Direct connection between two Dies and them connected to the I/O Die, don't we have the same we have right now??

The Master/Slave stuff is rather unlikely and don't think they'd do it...

 

 

 

If there wasn't a direct connection between the CPU Dies, why place them in Pairs of two??

You could have placed them whetever, however...

 

Quote

That's a though one, I never really looked at Bulldozer Opterons because they were DOA and K10 is getting rather old.

Basically, Bulldozer is K10 with a Changed Core attached...

The NB or I/O Stuff looks pretty much the same to K10 for some odd reason...

 

Quote

I think so? HyperTransport was used between sockets and was directly between the CPU/die but it's cache coherent so has to be written to a local cache of the remote CPU before any of the cores can use the data. Both CPUs must have the same cache data. To me that sounds like L3 cache would be used.

Yeah, that's how I darkly remember it as well, that its written to the L3 Cache first and then used inside the CPU...

[Taf the Ghost]

3 hours ago, wasab said:

10-15% ipc uplifts plus 0.5ghz high clock means roughly around Intel coffee lake performance maybe?

 

what is the current Intel CPU refresh lineup? I completely lost track after Intel derail from it's tick tock model and begin just refreshing one CPU after the another. 

It depends on the SKU. 2nd Gen Ryzen and Coffee Lake don't really have any IPC differences in most tasks already. It's really only code optimization that's different. There is a pretty hefty IPC lead for Intel in highly AVX2 optimized workloads, but AMD will eliminate or jump ahead of that with 3rd Gen Ryzen.

 

The rumor mill has settled on around 10% general IPC uplift and up to 100% in very specific instructions (probably around 25-30% in workstation-type loads that can leverage cores well). This wasn't really transfer straight to gaming, as that's going to be more clock dependent. Zen2 will also use less power, for the same amount of cores, by a fairly large margin. This is kind of why it's the King of the Rumor Mill for nearly a year. It'll be the first time AMD has a IPC, Node and Power advantage on Intel in the company's history. 

 

Oh, and these chips will be stupidly cheap for AMD to produce, so they can just extend their current price structure while increasing core counts at each range by a good chunk. The 16c parts, whenever they show up, will probably be in the 400-500USD range, but that'll also be twice as many cores as Intel wants you to pay that much for.

[Stefan Payne]

3 hours ago, Taf the Ghost said:

It'll be the first time AMD has a IPC, Node and Power advantage on Intel in the company's history. 

Without the Node it would be the second time.

In some workloads (=4 Core heavy load) even the 3rd as dual Core 2 Duo aka Quad was hindered by the FSB.

3 hours ago, Taf the Ghost said:

Oh, and these chips will be stupidly cheap for AMD to produce, so they can just extend their current price structure while increasing core counts at each range by a good chunk. The 16c parts, whenever they show up, will probably be in the 400-500USD range, but that'll also be twice as many cores as Intel wants you to pay that much for.

Yeah, I hope that as well.

Some people claim that it makes more sense to increase prices. I don't agree.

 

Right now Intel has Problems with Supply and Demand. With a low price, they have higher demand, thus can aim for more Marketshare and and also ruin the day on the other side, when they are ahead.

 

I really don't see any reason for high prices...

[GOTSpectrum]

13 hours ago, leadeater said:

not sure if there is any specific reasons why keeping it to 4 is best or preferred or increasing that a to be coming thing.

I read an article not long after zen first came out, they said that one of the big considerations for zen was limiting die-area. Hence the lack of a iGPU. They further went on to say that the reason the CCXs were only 4 cores was that to introduce a more traditional bus withing the CPU would increase the die area more than it was worth got the performance uplift, and that the high core count parts would have suffered due to the way inter-die communication would have worked with a more traditional bus... 

 

I've been trying to find the article for the last 40 mins but alas, I can not.

[GOTSpectrum]

13 minutes ago, Ben Quigley said:

I read an article not long after zen first came out, they said that one of the big considerations for zen was limiting die-area. Hence the lack of a iGPU. They further went on to say that the reason the CCXs were only 4 cores was that to introduce a more traditional bus withing the CPU would increase the die area more than it was worth got the performance uplift, and that the high core count parts would have suffered due to the way inter-die communication would have worked with a more traditional bus... 

 

I've been trying to find the article for the last 40 mins but alas, I can not.

To further add to this, 

 

They cared more about the high core count parts than the consumer products, naturally as they are the real money makers, and losing a small amount of performance on consumer AM4 to gain on EPYC(and TR, but this was less of a thought as TR was a side project) was an easy choice for them.

[Jito463]

On 4/30/2019 at 1:39 PM, Stefan Payne said:

for the AMD Hype, ASUS just released a statement about compatibility of 300 and 400 series Boards and Zen2, thought they don't name the names:

https://www.asus.com/News/EtaH71Hbjuio1arV

I see a list of names....

[Stefan Payne]

Just now, Jito463 said:

I see a list of names....

Yeah and I see something missing...

 

Hint:
A320...

[Jito463]

15 minutes ago, Stefan Payne said:

Yeah and I see something missing...

 

Hint:
A320...

Seems to me like the A series chipsets went by the wayside pretty quickly, as noted by the fact that there was never an A400 series.  Which makes some sense, because the B series weren't that much more and were better overall.