Why does DDR5 RAM has so much latency?

[Gat Pelsinger]

On the last Gen, DDR4 RAM kits, we can see CL timings from somewhere around 14 to 18, but on DDR5, on an average 5200 MHz kit, we see CL timings of 38! But why is it so? And why are we still seeing performance benefits?

[Eigenvektor]

CAS Latency is expressed in clock cycles, so don't be fooled by higher numbers. A higher number at a higher frequency can very well translate to the same absolute latency (in nanoseconds)

 

CL 16 at a transfer rate of 3200 MT/s translates to 10 ns

CL 38 at a transfer rate of 5200 MT/s translates to 14.6 ns

CL 40 at a transfer rate of 6000 MT/s translates to 13.3 ns

 

While that is a bit higher, you have to take into account that DDR5 is still a very new standard. We didn't have CL 16 DDR4 right at the start either.

 

~edit: Performance benefits depend on how latency vs bandwidth sensitive your use case is. If your use case primarily requires low latency (e.g. many small transfers) DDR5 might provide no benefit at all (at least for now). If it is bandwidth sensitive (e.g. few large transfers) the much higher transfer rate is going to benefit you.

 

E.g. while 13.3 vs 10 ns is a 33% increase in latency, your transfer at 6000 MT/s runs 87% faster than a 3200 MT/s, which might very well be enough to make up for the increased latency before the transfer started.

[RONOTHAN##]

DDR5 inherently has more bandwidth by the way it was designed. 

 

As for why the timings are so much looser on DDR5, that's the way it goes for every new DDR release. DDR3, for example, had kits going down to around CL8, whereas getting anything lower than CL12 on DDR4 is near impossible, but because DDR4 clocks so much higher the latency is much lower. We're in the weird transition period, where previous gen still has a significant latency advantage, but that will eventually pass as DDR5 clocks so much faster (DDR5 6400 CL32 is the same initial latency as DDR4 3200 CL16 but because it has so much more bandwidth, the performance will be better).