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AMD Hosting Zen Event at HotChips on Tuesday

DocSwag
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39 minutes ago, Thony said:

@DocSwag almost a day later and not a single word on what happened on Tuesday. Was AMD not giving any new info or what happened ? 

http://hexus.net/tech/news/cpu/96112-amd-provides-information-zen-hot-chips-28/

Not a lot more info imo. mentioned zen can be used in cpu tdp range from 25w to 100w. if we assume summit rigde is the highest zen, then 100w?

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Posted

here is the Video
 

 

//Case: Phanteks 400 TGE //Mobo: Asus x470-F Strix //CPU: R5 2600X //CPU Cooler: Corsair H100i v2 //RAM: G-Skill RGB 3200mhz //HDD: WD Caviar Black 1tb //SSD: Samsung 970 Evo 250Gb //GPU: GTX 1050 Ti //PSU: Seasonic MII EVO m2 520W

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Posted
On August 21, 2016 at 7:03 PM, Nicholatian said:

IPC improvements are magnitudes greater than 0.3%, not to mention Intel has been gradually upping clock rates as well since Sandy Bridge.

No, clock rates have stayed the same or most likely gone down. 5ghz has been the limit for many years. Clock speeds aren't everything either, remember that.

▓ƆԀ▓ S▓₱▓Ɇ▓c▓s▓: i7 6ʇɥפᴉƎ00K (4.4ghz), Asus DeLuxe X99A II, GT҉X҉1҉0҉8҉0 Zotac Amp ExTrꍟꎭe),Si6F4Gb D???????r PlatinUm, EVGA G2 Sǝʌǝᘉ5ᙣᙍᖇᓎᙎᗅᖶt, Phanteks Enthoo Primo, 3TB WD Black, 500gb 850 Evo, H100iGeeTeeX, Windows 10, K70 R̸̢̡̭͍͕̱̭̟̩̀̀̃́̃͒̈́̈́͑̑́̆͘͜ͅG̶̦̬͊́B̸͈̝̖͗̈́, G502, HyperX Cloud 2s, Asus MX34. פN∩SW∀S 960 EVO

Just keeping this here as a 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Posted
1 minute ago, Nicholatian said:

what are you talking about

They have most certainly gone up for most every locked chip I can think of. Look on Intel ARK lol

 

Maybe that’s true for overclocked chips, but only a tiny sliver of Intel’s customer base overclocks, so… haha

If you are looking at base clocks then I guess they have gone up but 5ghz seems to be the limit. Obviously LN2 and liquid helium will allow 9ghz but the xeons are still at 2.2ghz-3ghz.

▓ƆԀ▓ S▓₱▓Ɇ▓c▓s▓: i7 6ʇɥפᴉƎ00K (4.4ghz), Asus DeLuxe X99A II, GT҉X҉1҉0҉8҉0 Zotac Amp ExTrꍟꎭe),Si6F4Gb D???????r PlatinUm, EVGA G2 Sǝʌǝᘉ5ᙣᙍᖇᓎᙎᗅᖶt, Phanteks Enthoo Primo, 3TB WD Black, 500gb 850 Evo, H100iGeeTeeX, Windows 10, K70 R̸̢̡̭͍͕̱̭̟̩̀̀̃́̃͒̈́̈́͑̑́̆͘͜ͅG̶̦̬͊́B̸͈̝̖͗̈́, G502, HyperX Cloud 2s, Asus MX34. פN∩SW∀S 960 EVO

Just keeping this here as a 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Posted
1 hour ago, SamStrecker said:

If you are looking at base clocks then I guess they have gone up but 5ghz seems to be the limit. Obviously LN2 and liquid helium will allow 9ghz but the xeons are still at 2.2ghz-3ghz.

Xeons are not meant for home desktops anyway. And less than 5% people care about them so most of us dont look at their specs :D

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8 hours ago, Tomsen said:

It got 3 ALUs. It is shown in the core block diagram, in the documentation and just generally accepted as such. Where is it stated otherwise?

 

Never heard of using x86 instructions as measurement for OOOe width. That would depend on workload, can't just say random numbers, unless it is distinct caused by some kind of bottleneck in the microarchitecture. 

 

As for branch predictors and their accuracy, obviously marketing has had their fingers in the numbers. Else branches wouldn't be a problem.

 

They were buggy, I can't say anything about how it is today. Good thing there wasn't any bad code, he did end up single out the issue so he could replicate it to verify it was a bug (it didn't behave as the documentation stated it should). I haven't heard about enterprise been happy for intels iGP (only the opposite), and those mega corporations don't use the same public documentation/information as others do, often relying on things they discovered themselves or was told in confidence. 

 

You don't need to add it to the list, it is already under the "intel added igp to sandy".

 

http://www.tomshardware.com/reviews/Intel-i7-nehalem-cpu,2041-3.html

"With the Nehalem architecture, Intel has improved the functionality of the Loop Stream Detector. First of all the buffer is larger—it can now store 28 instructions. But what’s more, its position in the pipeline has changed. In Conroe, it was located just after the instruction fetch phase. It’s now located after the decoders; this new position allows a larger part of the pipeline to be disabled. The Nehalem’s Loop Stream Detector no longer stores x86 instructions, but rather µops."

 

We can both play a game of name a wizard, but that doesn't prove anything yet. Because all code is simple loops.. Also that is not new news.. Loops are perfect for vectors, because guess what, often small code sample, get repeated over and over, and if no dependencies are in place there are basically no issues. That is however far from normal code.

 

Patrick, of course the necessary internal registers updated at the same frequency, else it wouldn't work one bit.

Yes, it takes time for the data to come back from the ALU, however that is a non-issue, the same way it takes time for the data to come into the ALU.

Or are you saying they clocked it 2x the normal clockspeed for nothing, since nothing got accomplished in less than a normal clockcycle?

 

Yes, it was clocked at double for nothing, and that's the fundamental problem. Making one piece move any faster than fundamental limits of data transformation and signaling is pointless, as there's no benefit. Intel can't make two Ints add in under 1 cycle. If you want to qualify that with "in a way that's useful," fine, but you're being pedantic.

 

It's not just simple loops. It's dynamic programming and iterative divide and conquer. Tail recursion is also detectable. Your understanding of the hardware is still incredibly limited, and no, it's two ALUs. Read the documentation I provided to Doc Swag shortly above.

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11 minutes ago, patrickjp93 said:

Yes, it was clocked at double for nothing, and that's the fundamental problem. Making one piece move any faster than fundamental limits of data transformation and signaling is pointless, as there's no benefit. Intel can't make two Ints add in under 1 cycle. If you want to qualify that with "in a way that's useful," fine, but you're being pedantic.

Oh, so if they had the ALU's clocked at the same rate as the core, it would yield the same performance? What exactly are you stating?

They aren't moving any pieces faster than any fundamental limits, where are you getting this from?

You are going into semantics. Let me explain this again; Intel had their ALUs clocked 2x the rate of the core, so normal instruction with 1clk latency would in relative to the core be executed in 0.5clk, but in 1clk in relative to the ALU.

 

11 minutes ago, patrickjp93 said:

It's not just simple loops. It's dynamic programming and iterative divide and conquer. Tail recursion is also detectable. Your understanding of the hardware is still incredibly limited

I have never said I know of the inner working to detail of Intel core architecture. I know what is publicly published and written about, and a few tidbits through social /work circles. I know what I know, and I also know what I don't know. I don't write out about things I don't know about (atleast not without clarifying it somehow).

Do you think you know the inner working? That which are not publicly published nor publicly written about.

Funny how whenever someone request a source on some dubious statement you made, you turn it into a game of where's wally. If we are so lucky for you to drop a link, it either goes to a 50+ page paper with no clear direction or a source directly stating against you.

 

11 minutes ago, patrickjp93 said:

it's two ALUs. Read the documentation I provided to Doc Swag shortly above.

I just did.. (atleast the relevant section: 3.3)

 

Quote

Nehalem Issue Ports and Execution Units The URS scheduler can dispatch up to six micro-ops per cycle through the six issue ports to the execution engine which can execute up to 6 operations per clock cycle, namely

• 3 memory operations (1 integer and FP load, 1 store address and 1 store data) and

• 3 arithmetic/logic operations

 

Quote

the EUs associated with each port are the following:

Port 0 supports

• Integer ALU and Shift Units

• Integer SIMD ALU and SIMD shuffle

• Single precision FP MUL, double precision FP MUL, FP MUL (x87), FP/SIMD/SSE2 Move and Logic and FP Shuffle, DIV/SQRT

 

Port 1 supports

• Integer ALU, integer LEA and integer MUL

• Integer SIMD MUL, integer SIMD shift, PSAD and string compare, and

• FP ADD

 

Port 5 Supports

• Integer ALU and Shift Units, jump

• Integer SIMD ALU and SIMD shuffle

• FP/SIMD/SSE2 Move and Logic

 

There is nothing stating otherwise in that section, and I doubt it will in others.

Have you even read the paper yourself?

Please avoid feeding the argumentative narcissistic academic monkey.

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3 hours ago, Tomsen said:

Oh, so if they had the ALU's clocked at the same rate as the core, it would yield the same performance? What exactly are you stating?

They aren't moving any pieces faster than any fundamental limits, where are you getting this from?

You are going into semantics. Let me explain this again; Intel had their ALUs clocked 2x the rate of the core, so normal instruction with 1clk latency would in relative to the core be executed in 0.5clk, but in 1clk in relative to the ALU.

 

I have never said I know of the inner working to detail of Intel core architecture. I know what is publicly published and written about, and a few tidbits through social /work circles. I know what I know, and I also know what I don't know. I don't write out about things I don't know about (atleast not without clarifying it somehow).

Do you think you know the inner working? That which are not publicly published nor publicly written about.

Funny how whenever someone request a source on some dubious statement you made, you turn it into a game of where's wally. If we are so lucky for you to drop a link, it either goes to a 50+ page paper with no clear direction or a source directly stating against you.

 

I just did.. (atleast the relevant section: 3.3)

 

 

 

There is nothing stating otherwise in that section, and I doubt it will in others.

Have you even read the paper yourself?

Yes

 

If the whole pipeline can't use the information as quickly as it's produced, the end result is if that information had been produced at the same speed as everything else. The fundamental limit is the system.

 

This is publicly available information. It's in the x86 optimization manuals, and those are 2000+ page documents.

 

You're incorrectly reading that section. There are 2 ALUs, but they can be dispatched to by 3 ports in the scheduler. That's part of what makes it a CISC architecture.

 

Yes there is. Read it again, slowly.

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1 hour ago, patrickjp93 said:

Yes

 

If the whole pipeline can't use the information as quickly as it's produced, the end result is if that information had been produced at the same speed as everything else. The fundamental limit is the system.

 

This is publicly available information. It's in the x86 optimization manuals, and those are 2000+ page documents.

 

You're incorrectly reading that section. There are 2 ALUs, but they can be dispatched to by 3 ports in the scheduler. That's part of what makes it a CISC architecture.

 

Yes there is. Read it again, slowly.

Patrick, it is quite obvious you are just running in circles, trying to "win" by repeating yourself until the other part cannot be arsed to argue against you anymore. Despite you actually being wrong in several times already.

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57 minutes ago, Prysin said:

Patrick, it is quite obvious you are just running in circles, trying to "win" by repeating yourself until the other part cannot be arsed to argue against you anymore. Despite you actually being wrong in several times already.

Except I'm not wrong! Jesus Christ it's here in black and white! Just because 3 execution ports have ALU options does not mean there are 3 ALUs! If you look at the block diagram, there are only 2!

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4 hours ago, patrickjp93 said:

Yes

 

If the whole pipeline can't use the information as quickly as it's produced, the end result is if that information had been produced at the same speed as everything else. The fundamental limit is the system.

 

This is publicly available information. It's in the x86 optimization manuals, and those are 2000+ page documents.

 

You're incorrectly reading that section. There are 2 ALUs, but they can be dispatched to by 3 ports in the scheduler. That's part of what makes it a CISC architecture.

 

Yes there is. Read it again, slowly.

It leaves me in wonder how Intel engineers couldn't see that?

 

I never said that the whole core pipeline can use the information as quickly. I never stated that it could, and sadly it doesn't further your point one bit.

The end result can still be produced at 2x the speed relative to the core clock. You are more concerned about when the result is committed.

But it never goes beyond it. I don't even understand why you think so.

 

Yet, nothing publicly information state as such? Why can't you find anything to support your statement? Why do you suddenly go for another source (another game of where's wallly/waldo).

 

I didn't misinterpreted anything in that section. In fact, that section is overwhelmingly supportive of what I have stated so far.

I even single out out the relevant information in regards to our discussion in my previous reply. Why don't you go ahead and do that?

I don't even think you understand what makes something a CISC architecture anymore, you are just spewing random nonsense now.

 

There is nothing, nothing at all in that section. You better copy & paste the relevant bits, quote it, link the source. 

 

2 hours ago, Prysin said:

Patrick, it is quite obvious you are just running in circles, trying to "win" by repeating yourself until the other part cannot be arsed to argue against you anymore. Despite you actually being wrong in several times already.

My guess is he is stalling for time. He needs the hair to grow out again before another haircut.

 

1 hour ago, patrickjp93 said:

Except I'm not wrong! Jesus Christ it's here in black and white! Just because 3 execution ports have ALU options does not mean there are 3 ALUs! If you look at the block diagram, there are only 2!

It is here in black and white? Should make is very easy to copy & paste, but yet, here you are acting like donald trump "I hear".

All block diagram shows exactly 3 ALUs.

Please avoid feeding the argumentative narcissistic academic monkey.

"the last 20 percent – going from demo to production-worthy algorithm – is both hard and is time-consuming. The last 20 percent is what separates the men from the boys" - Mobileye CEO

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@patrickjp93 and @Tomsen this really is getting quite unnecessary on the ALU thing.... Obviously one of you is right and one of you is wrong but only "claiming" the diagram says something is not gonna resolve this. Why don't both of you take the diagram and show the other where you got it from, then use paint or something to draw exactly where it signals that a Nehalem core has 2 or 3 ALUs. Because arguing the way you are right now is gonna do nothing.

Make sure to quote me or tag me when responding to me, or I might not know you replied! Examples:

 

Do this:

Quote

And make sure you do it by hitting the quote button at the bottom left of my post, and not the one inside the editor!

Or this:

@DocSwag

 

Buy whatever product is best for you, not what product is "best" for the market.

 

Interested in computer architecture? Still in middle or high school? P.M. me!

 

I love computer hardware and feel free to ask me anything about that (or phones). I especially like SSDs. But please do not ask me anything about Networking, programming, command line stuff, or any relatively hard software stuff. I know next to nothing about that.

 

Compooters:

Spoiler

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Laptop (I use it for school):

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And if you're curious (or a stalker) I have a Just Black Pixel 2 XL 64gb

 

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48 minutes ago, DocSwag said:

@patrickjp93 and @Tomsen this really is getting quite unnecessary on the ALU thing.... Obviously one of you is right and one of you is wrong but only "claiming" the diagram says something is not gonna resolve this. Why don't both of you take the diagram and show the other where you got it from, then use paint or something to draw exactly where it signals that a Nehalem core has 2 or 3 ALUs. Because arguing the way you are right now is gonna do nothing.

It is simply one of his dubious statement on the run. I didn't thought it would be necessary, as simply googling nehalem core block will only give your result showing 3 ALUs.

But okay then.. Don't want to edit the images as I'm on the run at this time, but look at port 0, 1 & 5, all leading to algorithm/logic execution unit, and no documentation, no written about one being mislabeled as ALU instead of AGU.

 

Some links to pictures;

Spoiler

http://pc.watch.impress.co.jp/docs/2008/0424/kaigai_02l.gif

http://www.hpcresearch.nl/euroben/Overview/web11/nehalem.jpg

http://sc.tamu.edu/Images/NehalemEU.png

https://upload.wikimedia.org/wikipedia/commons/6/64/Intel_Nehalem_arch.svg

 

Even his own source a few replies back, stated directly against him:

http://sc.tamu.edu/systems/eos/nehalem.pdf (see figure 5 on page 14) (direct link here: http://sc.tamu.edu/Images/NehalemEU.png)

Do also see the things I quoted from the same paper.

Please avoid feeding the argumentative narcissistic academic monkey.

"the last 20 percent – going from demo to production-worthy algorithm – is both hard and is time-consuming. The last 20 percent is what separates the men from the boys" - Mobileye CEO

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On 8/25/2016 at 8:10 AM, patrickjp93 said:

Except I'm not wrong! Jesus Christ it's here in black and white! Just because 3 execution ports have ALU options does not mean there are 3 ALUs! If you look at the block diagram, there are only 2!

 

Still waiting for you to present it in black and white. Show the black diagram where it shows only 2.

The source you used back a few replies ago showed 3 in their block diagram.

 

Please do use the quote function to copy paste any necessary information that might support your statement, and link to (and perhaps help with a few directions like what page or section if it is a longer report) your source.

 

Currently, you have showed nothing to support your statement in this thread.

Please avoid feeding the argumentative narcissistic academic monkey.

"the last 20 percent – going from demo to production-worthy algorithm – is both hard and is time-consuming. The last 20 percent is what separates the men from the boys" - Mobileye CEO

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