Intel's 10nm technology presented + Solving manufacturing naming mess (Intel's way)

[agent_x007]

Company presented it's 10nm wafers to public during Intel's Technology and Manufacturing Day in Beijing.

Quote

Intel’s 10 nm technology has the world’s tightest transistor and metal pitches, created with hyper scaling, for the highest density in the industry. Hyper scaling is a term used by Intel to describe the 2.7x logic transistor density improvement attained on the company’s 14 nm and 10 nm processes. And, for the first time, Intel’s “Cannon Lake” 10 nm wafer was on public display.

Source : LINK,



More graphs comparing 10nm to older tech : LINK.
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Mark Bohr's (Intel) take on transistor manufacturing naming mess :

Quote

It’s time to resurrect a metric that was used in the past but fell out of favor several nodes ago. It is based on the transistor density of standard logic cells and includes weighting factors that account for typical designs. While there is a large variety of standard cells in any library, we can take one ubiquitous, very simple one – a 2-input NAND cell (4 transistors) – and one that is more complex but also very common: a scan flip flop (SFF). This leads to a previously accepted formula for transistor density:

(The weightings 0.6 and 0.4 reflect the ratio of very small and very large cells in typical designs.)

Every chip maker, when referring to a process node, should disclose its logic transistor density in units of MTr/mm2 (millions of transistors per square millimeter) as measured by this simple formula. Reverse engineering firms can readily verify the data.

There is one important measure missing: SRAM cell size. Given the wide variety of SRAM-to-logic ratios in different chips, it is best to report SRAM cell size separately, next to the NAND+SFF density metric.

By adopting these metrics, the industry can clear up the node naming confusion and focus on driving Moore’s Law forward.

Source : LINK

[Fahim Foysal]

Hopefully the performance improvement will be higher than a massive 7% like previous gen upgrades.

[Bananasplit_00]

im starting to think the two new cores might be because a quad core die at 10nm was simply too small to cool well

[Sauron]

So I zoomed into that wafer and enhanced the image with my hacking moves bypassing the firewall and I managed to get a clear picture of what the die looks like:

Spoiler

 

Oh wait that's just sandy bridge again. It's easy to get confused lately.

 

[Bananasplit_00]

35 minutes ago, Sauron said:

So I zoomed into that wafer and enhanced the image with my hacking moves bypassing the firewall and I managed to get a clear picture of what the die looks like:

  Hide contents

Oh wait that's just sandy bridge again. It's easy to get confused lately.

 

i thought Sandybridge didnt have the FIVR? how can you mistake the two...