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The pace of obsolescence.

IKnight
Just now, Ben Quigley said:

Why is called 14nm then? Genuinely curious here

To be totally honest , i don't really know what is used to define nodes when dealing with finfet . Historically , planar technology used gate pitch as the primary measurement . The ITRS defines nodes somewhat loosely ( what they should be called ,eg 22nm , 14nm etc ) , but each node technically HAS to shrink every feature by x0.7 vs the previous node . Couple that with the fact that more and more companies use these measurements for marketing rather than reflecting actual size ( samsung and tsmc for example ), and you realize that it's more and more vague .

All i can say is that gate pitch isn't used as anymore , as intel 14nm has a 20nm gate pitch .

But it's worth noting that absolute size isn't the biggest concern anyway . Smaller transistors no longer use less power than larger ones .

It doesn't even fully dictate design density either , as that also impacted by process leakage and power.

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