xeon phi Intel begins to ship its KNL Xeon Phi processors

[porina]

30 minutes ago, patrickjp93 said:

http://www.realworldtech.com/haswell-cpu/4/

From the above link "One interesting point is that while Haswell can execute two 256-bit FMAs or FMULs per cycle, there is still only a single 256-bit FADD." which still suggests to me they're separate units. 

30 minutes ago, patrickjp93 said:

Your analysis of the cache is also incomplete. If you're doing 1 operation over a large dataset, then yes, memory streaming will be necessary, but what about a lot of transformations on a small dataset?

For small enough datasets, it can run within L3 cache at what I call practically (ram) unlimited performance. I use that condition to examine the behaviour of the architecture without worrying about ram impact. Over at PrimeGrid there is a challenge on right now, running tasks with 256k FFT size. This translates into 2MB per task, and most run one task per core. Now, this isn't the complete story, as that is only the FFT data, and doesn't consider any other data. I understand it also uses lookup tables for some things for example, so "a bit more" is required. And this came out when I looked at how performance varied with architecture after clock normalisation. 2MB/core was quite a bit better than 1.5MB/core (Skylake+Haswell). More recently I got a Xeon with 2.5MB/core, and that had a slight improvement over 2Mb/core within the Haswell family. I don't have the exact numbers on me right now.

[patrickjp93]

1 hour ago, porina said:

From the above link "One interesting point is that while Haswell can execute two 256-bit FMAs or FMULs per cycle, there is still only a single 256-bit FADD." which still suggests to me they're separate units. 

For small enough datasets, it can run within L3 cache at what I call practically (ram) unlimited performance. I use that condition to examine the behaviour of the architecture without worrying about ram impact. Over at PrimeGrid there is a challenge on right now, running tasks with 256k FFT size. This translates into 2MB per task, and most run one task per core. Now, this isn't the complete story, as that is only the FFT data, and doesn't consider any other data. I understand it also uses lookup tables for some things for example, so "a bit more" is required. And this came out when I looked at how performance varied with architecture after clock normalisation. 2MB/core was quite a bit better than 1.5MB/core (Skylake+Haswell). More recently I got a Xeon with 2.5MB/core, and that had a slight improvement over 2Mb/core within the Haswell family. I don't have the exact numbers on me right now.

The author is making a small mistake. The core can process 2 instructions, but can only execute one of them per cycle. Or he's confusing the fact that FMA is itself 2 ops.

[Belgarathian]

On 6/22/2016 at 4:12 AM, sof006 said:

Jesus... Thats a lot of cores. Wonder how many of them you'd need to make a 100 Petabyte machine...

 

On 6/22/2016 at 4:16 AM, FloRolf said:

Wtf is a 100petabyte machine? 

 

On 6/22/2016 at 4:45 AM, sof006 said:

Super computer

You mean Petaflop - And I'm assuming your comment is in relation to the Chinese super computer they've just finished building? - Source: http://arstechnica.com/information-technology/2013/06/chinese-supercomputer-destroys-speed-record-and-will-get-much-faster/

[mikat]

On 6/21/2016 at 6:27 PM, Bouzoo said:

That doesn't make it any better. It's just who is the lesser evil out of 2. 

 

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[CameronP90]

Inb4 next holy sh!t ep? D: