Micron Rev E overclock from 3200 to 3600 memory errors

[Hans Power]

So, I tried overclocking my Crucial Ballistix 2x16 3200Mhz Rev E memory kit to 3600Mhz. I just used the XMP timings which the respective 3600 memory kit would have which would be 16-18-18-38 and tRC 58 and left the other subtimings on auto (Stock XMP for 3200: 16-18-18-36, tRC 74). So, first Memtest86 run passed but the second one threw an error. So, what's the first place to start to get it 100% stable, specifically for Micron Rev E? CL, tRCD, tRP, TRAS or tRC or even voltage? Mind you, that I wouldn't want to touch voltage if at all possible.

[Stahlmann]

I'd first set the voltage to 1.45 and see if it's stable there. If it still doesn't work, then work on the timings.

[Levent]

I suggest you to use Ryzen Dram Calculator, its gives you really good starting point.

[Hans Power]

1 minute ago, Stahlmann said:

I'd first set the voltage to 1.45 and see if it's stable there. If it still doesn't work, then work on the timings.

I'd rather not if I can slightly increase timings instead. I want to sustain longevity, especially now.

[Stahlmann]

1 minute ago, Hans Power said:

I'd rather not if I can slightly increase timings instead. I want to sustain longevity, especially now.

I ran my memory at 1.45V all day. I also had Ballistix memory running at 3600MHz cl14 this way. No errors, no instability.

[ForwardVoltage]

Couple things:
- Ballistix, they're not temperature sensitive (can run up to 70C and be fine)
- Most Ballistix users OC daily 1.5v here. It stops being safe around 1.7v. That being said, only frequency and tCL are tied to voltage as in if you shove more power, only those two settings clock better.
- DRAM Calculator is just wrong sometimes...Instead of trying to train CL14, let's just use CL15 with GDM Off?????

If you haven't already (Yes, I can read your signature, but I want to be sure), can you either load up Thaiphoon Thruster to look at the PCB Revision (I don't care about what the die stepping is since it can only be SR 16Gbit Rev.B or DR 8Gbit Rev.E or SR 16Gbit Rev.E) or just look underneath the heatspreaders to see if you can find two rows of dram wafers?

Clocking wise, there is no reason why a normal set of Ballistix wouldn't hit above 3600 there. This IC, afterall, has such a high frequency cap (or maybe not) that we literally cannot know where it stops since our IMCs are the limiting factor. The reason why you didn't past the test is probably because the auto subtimings are not good. 

What I would do first is actually loosen everything manually (by a lot), all primary, secondary, and tertiary timings. Most x86 and other bit based systems nowadays are built for transfer bandwidth of which channel count and frequency of our DRAM is most affected by. Let's try to get the highest sync'ed frequency before we tighten timings since that's actually going to reduce our latency (higher FCLK is better too). 

5600x should be able to do between 1867 and 2000 FCLK while still being 1:1:1 with MCLK and UCLK. Go to BIOS and set a manual FCLK to 1866, vDIMM or DRAM Voltage to 1.5v, vSoC to 1.15, if you want to use Medium LLC for SoC--fine by me, some vCore like 1.25v is fine, and set FCLK == MCLK == UCLK. I would also set VDDG IOD and VDDG CCD to 1090 or 1.09v (this helps with FCLK stability). 

I also wouldn't use memtest86 because it's too slow to catch errors. I much prefer the anta-profile on TM5 or SSE/AVX2 on OCCT. TM5 will primarily hit your RAM in a different way from other programs and OCCT is great all-around tester for RAM, CPU, and FCLK. I'd hit it with a 30 minute session of SSE OCCT and 30 minutes of AVX2, and see if it's stable. 

If it's stable there, push up to 1900 mHz FCLK, keep all the voltages the same, and test again (make sure timings are still loose). Then to 1933 or you can skip to 2000. I haven't personally tested MSI on B550 but it seems like only newer-revisions of Asus (B550 + Dark Hero, no X570) hit 2000 FCLK consistently. 

If we're stable at 2000, great! Now we can start by setting timings. If your kit is really dual rank, we're going to have leave tRFC loose for right now and focus on primary timings. With Gear Down Mode (GDM) and Power Down Mode off:
- tCL = 20
- tRCDRD = 22
- tRCDWR = 22 (this can be significantly tightened to probably 8-10)
- tRP = 25
- tRAS = 40
- tRC = 70
- tRRDS = 10
- tRRDL = 12
- tFAW = 34
- tRFC = 620
- tCWL = 18
- ProcODT = Auto
- ODT (parks) = Auto

The goal is going to be reducing this. tCL can hopefully snag tCL 16, but we'll have to get there. tFAW can be probably tightened to 24 or less. tRFC around 290ns (where tXX/frequency * 2000 = ns) would be cool (assuming DR RevE). Ballistix cannot do as tight tRCDRD as S8B can under OC, but tRCDWR can. tRP, tRAS, and tRC sometimes have latency penalties associated with them; however, as seen per this reddit post, it can sometimes be largely ignored and just try to set the lowest timings. 

With all this information, let me know if you need help. Here is a r/OC spreadsheet of user submitted Zen 3 (and other Zens) OCs

[Hans Power]

7 hours ago, ForwardVoltage said:

Couple things:
- Ballistix, they're not temperature sensitive (can run up to 70C and be fine)
- Most Ballistix users OC daily 1.5v here. It stops being safe around 1.7v. That being said, only frequency and tCL are tied to voltage as in if you shove more power, only those two settings clock better.
- DRAM Calculator is just wrong sometimes...Instead of trying to train CL14, let's just use CL15 with GDM Off?????

If you haven't already (Yes, I can read your signature, but I want to be sure), can you either load up Thaiphoon Thruster to look at the PCB Revision (I don't care about what the die stepping is since it can only be SR 16Gbit Rev.B or DR 8Gbit Rev.E or SR 16Gbit Rev.E) or just look underneath the heatspreaders to see if you can find two rows of dram wafers?

Clocking wise, there is no reason why a normal set of Ballistix wouldn't hit above 3600 there. This IC, afterall, has such a high frequency cap (or maybe not) that we literally cannot know where it stops since our IMCs are the limiting factor. The reason why you didn't past the test is probably because the auto subtimings are not good. 

What I would do first is actually loosen everything manually (by a lot), all primary, secondary, and tertiary timings. Most x86 and other bit based systems nowadays are built for transfer bandwidth of which channel count and frequency of our DRAM is most affected by. Let's try to get the highest sync'ed frequency before we tighten timings since that's actually going to reduce our latency (higher FCLK is better too). 

5600x should be able to do between 1867 and 2000 FCLK while still being 1:1:1 with MCLK and UCLK. Go to BIOS and set a manual FCLK to 1866, vDIMM or DRAM Voltage to 1.5v, vSoC to 1.15, if you want to use Medium LLC for SoC--fine by me, some vCore like 1.25v is fine, and set FCLK == MCLK == UCLK. I would also set VDDG IOD and VDDG CCD to 1090 or 1.09v (this helps with FCLK stability). 

I also wouldn't use memtest86 because it's too slow to catch errors. I much prefer the anta-profile on TM5 or SSE/AVX2 on OCCT. TM5 will primarily hit your RAM in a different way from other programs and OCCT is great all-around tester for RAM, CPU, and FCLK. I'd hit it with a 30 minute session of SSE OCCT and 30 minutes of AVX2, and see if it's stable. 

If it's stable there, push up to 1900 mHz FCLK, keep all the voltages the same, and test again (make sure timings are still loose). Then to 1933 or you can skip to 2000. I haven't personally tested MSI on B550 but it seems like only newer-revisions of Asus (B550 + Dark Hero, no X570) hit 2000 FCLK consistently. 

If we're stable at 2000, great! Now we can start by setting timings. If your kit is really dual rank, we're going to have leave tRFC loose for right now and focus on primary timings. With Gear Down Mode (GDM) and Power Down Mode off:
- tCL = 20
- tRCDRD = 22
- tRCDWR = 22 (this can be significantly tightened to probably 8-10)
- tRP = 25
- tRAS = 40
- tRC = 70
- tRRDS = 10
- tRRDL = 12
- tFAW = 34
- tRFC = 620
- tCWL = 18
- ProcODT = Auto
- ODT (parks) = Auto

The goal is going to be reducing this. tCL can hopefully snag tCL 16, but we'll have to get there. tFAW can be probably tightened to 24 or less. tRFC around 290ns (where tXX/frequency * 2000 = ns) would be cool (assuming DR RevE). Ballistix cannot do as tight tRCDRD as S8B can under OC, but tRCDWR can. tRP, tRAS, and tRC sometimes have latency penalties associated with them; however, as seen per this reddit post, it can sometimes be largely ignored and just try to set the lowest timings. 

With all this information, let me know if you need help. Here is a r/OC spreadsheet of user submitted Zen 3 (and other Zens) OCs

Nice! That was very detailed! Actually I managed to get it Memtest86 stable with stock voltages by increasing tRCDRD from 18 to 19. But it still throws errors in OCCT. So I just increased DRAM Voltage to 1.4 and am running OCCT Memtest again.

[Hans Power]

7 hours ago, ForwardVoltage said:

Couple things:
- Ballistix, they're not temperature sensitive (can run up to 70C and be fine)
- Most Ballistix users OC daily 1.5v here. It stops being safe around 1.7v. That being said, only frequency and tCL are tied to voltage as in if you shove more power, only those two settings clock better.
- DRAM Calculator is just wrong sometimes...Instead of trying to train CL14, let's just use CL15 with GDM Off?????

If you haven't already (Yes, I can read your signature, but I want to be sure), can you either load up Thaiphoon Thruster to look at the PCB Revision (I don't care about what the die stepping is since it can only be SR 16Gbit Rev.B or DR 8Gbit Rev.E or SR 16Gbit Rev.E) or just look underneath the heatspreaders to see if you can find two rows of dram wafers?

Clocking wise, there is no reason why a normal set of Ballistix wouldn't hit above 3600 there. This IC, afterall, has such a high frequency cap (or maybe not) that we literally cannot know where it stops since our IMCs are the limiting factor. The reason why you didn't past the test is probably because the auto subtimings are not good. 

What I would do first is actually loosen everything manually (by a lot), all primary, secondary, and tertiary timings. Most x86 and other bit based systems nowadays are built for transfer bandwidth of which channel count and frequency of our DRAM is most affected by. Let's try to get the highest sync'ed frequency before we tighten timings since that's actually going to reduce our latency (higher FCLK is better too). 

5600x should be able to do between 1867 and 2000 FCLK while still being 1:1:1 with MCLK and UCLK. Go to BIOS and set a manual FCLK to 1866, vDIMM or DRAM Voltage to 1.5v, vSoC to 1.15, if you want to use Medium LLC for SoC--fine by me, some vCore like 1.25v is fine, and set FCLK == MCLK == UCLK. I would also set VDDG IOD and VDDG CCD to 1090 or 1.09v (this helps with FCLK stability). 

I also wouldn't use memtest86 because it's too slow to catch errors. I much prefer the anta-profile on TM5 or SSE/AVX2 on OCCT. TM5 will primarily hit your RAM in a different way from other programs and OCCT is great all-around tester for RAM, CPU, and FCLK. I'd hit it with a 30 minute session of SSE OCCT and 30 minutes of AVX2, and see if it's stable. 

If it's stable there, push up to 1900 mHz FCLK, keep all the voltages the same, and test again (make sure timings are still loose). Then to 1933 or you can skip to 2000. I haven't personally tested MSI on B550 but it seems like only newer-revisions of Asus (B550 + Dark Hero, no X570) hit 2000 FCLK consistently. 

If we're stable at 2000, great! Now we can start by setting timings. If your kit is really dual rank, we're going to have leave tRFC loose for right now and focus on primary timings. With Gear Down Mode (GDM) and Power Down Mode off:
- tCL = 20
- tRCDRD = 22
- tRCDWR = 22 (this can be significantly tightened to probably 8-10)
- tRP = 25
- tRAS = 40
- tRC = 70
- tRRDS = 10
- tRRDL = 12
- tFAW = 34
- tRFC = 620
- tCWL = 18
- ProcODT = Auto
- ODT (parks) = Auto

The goal is going to be reducing this. tCL can hopefully snag tCL 16, but we'll have to get there. tFAW can be probably tightened to 24 or less. tRFC around 290ns (where tXX/frequency * 2000 = ns) would be cool (assuming DR RevE). Ballistix cannot do as tight tRCDRD as S8B can under OC, but tRCDWR can. tRP, tRAS, and tRC sometimes have latency penalties associated with them; however, as seen per this reddit post, it can sometimes be largely ignored and just try to set the lowest timings. 

With all this information, let me know if you need help. Here is a r/OC spreadsheet of user submitted Zen 3 (and other Zens) OCs

Also just checked Taiphoon Burner and it is indeed Rev E or E-Die. I already noticed that it's Dual Rank and that the product description ends with M16FE which indicates Rev E. Thanks again of all the details - I gonna dive into it eventually but for now I'd be content to reach 3600 without too much of a timing penalty.

[Hans Power]

Alright, so far no errors after half an hour of OCCT memory test with CL 16, tRCDRD 19, tRCDWR 18, tRP 18, tRAS 38 and tRC 58 @1.4v. Everything else is still on auto. I'll let it run the full hour, though, just to make sure.

[ForwardVoltage]

28 minutes ago, Hans Power said:

Alright, so far no errors after half an hour of OCCT memory test with CL 16, tRCDRD 19, tRCDWR 18, tRP 18, tRAS 38 and tRC 58 @1.4v. Everything else is still on auto. I'll let it run the full hour, though, just to make sure.

 

Are you at 4000 MT/s with 2000 MHz FCLK?

[Hans Power]

Just now, ForwardVoltage said:

 

Are you at 4000 MT/s with 2000 MHz FCLK?

Noo, still trying to get 3600 stable, lol. Unfortunately it threw errors at the last 6 minutes so increased the voltage slightly. Btw, do I run the risk of early degredation when I go up to, let's say 1.45v or even 1.5v? This system needs to run for the next 6 years at least and I want 100% stability if at all possible.

[Hans Power]

Even at 1.45v I still got memory errors for the second run. I think I gonna go back to XMP. I'm really not keen on degrading my chips early on by putting loads of voltage through them since hardware these days is becoming unobtanium. Maybe I get back to (memory) overclocking as soon as my chips hit a performance wall for what I want to do which should be still a few years away.

[ForwardVoltage]

On 3/2/2021 at 12:39 AM, Hans Power said:

Even at 1.45v I still got memory errors for the second run. I think I gonna go back to XMP. I'm really not keen on degrading my chips early on by putting loads of voltage through them since hardware these days is becoming unobtanium. Maybe I get back to (memory) overclocking as soon as my chips hit a performance wall for what I want to do which should be still a few years away.

Alright, cheers.

[Nena Trinity]

Setting up voltage is not much risk to the RAM, its a slightly bigger risk on the memory controller but then we have people like Buildzoid who never managed to blew up a single 14nm CPU... His go to strat is 1.5v out of box! Now we all know Intel have stated in the past for Skylake that anyhting over 1.35v can damage the IMC but to be fair that is unlikely and is just them trying to cover thier asses if somehting goes wrong... UwU

 

Try 1.4v? Or try to increase it to 17-19-19-39 on the timings?

 

Logical way of doing it:

*3600MHz CL16-18-18

*3800MHz CL17-19-19 (GDM will make it 18-19-19)

*4000MHz CL18-20-20 (Might have to go to 21 or 22 here)

*4000+ *Infinity Fabric Rage Quits The Chat*

[enormitysz]

@ForwardVoltage I purposely made an account to tell you how much of a good dude you are. The world needs more people like you let alone more people willing to actually give someone who needs their help troubleshooting an issue their them time or day. Respect @ForwardVoltage, your good deed will never go unnoticed as I shall always remember your legacy.

[chouwa]

@ForwardVoltageI also made an account to solely congratulate you as one of my role models. I will follow you into the far reaches of PC building. Where Voltage pushes I will flow.