Google Sponsoring Free Open Source Chip Tapeouts

[WelshFruitSnacks]

 

Summary

Google is trying to open up the chip design market by partnering with Skywater Technology Foundry (Formerly owned by Cypress Semiconductor) to release their 130nm PDK on github. Other contributors include OSU and Efabless.

 

This includes STD Cell libraries, a RAM compiler, DRC's, and additional tooling needed to take RTL to the GDS level.

The primary PnR(Place and Route) tool is Magic and they are trying to tape out Strive RISC V Soc's with this kit as a test.

Don't remember what they are planning for low level synthesis.

 

Currently Analog Cells+Primitives are unavailable. No PLL's, no ADC, DAC. I guess you could see if the RAM compiler can spit out sense amps you can create a ADC with.

 

In the YouTube live-stream Tim Ansell announced Google would be sponsoring a shuttle in November and maybe more in the future. Designs can be up to 10mm^2 and each shuttle will include 40 designs.

The designs will be taped out and packaged at no cost. But must be willing to publish everything from RTL to GDS to github with an open source liscene

 

Quotes

Quote

"[Its harder for small teams to hardware accelerate their workloads ... Google wants every team to be able to hardware accelerate their workloads]"

 

My thoughts

As a Physical Design Engineer I think this is going to be fun if it takes off since I can learn about other parts of my work independently. Improvements to the STD Cell library, working on Timing and correlation, lots of possibilities. Someone might just want to submit a design full of ring oscillators for each STD cell to correlate the Library with the data.

 

For Software focused engineers you can now start thinking about ASICs for your own workloads.

 

 

Sources

https://github.com/google/skywater-pdk

https://hackaday.com/2020/06/25/creating-a-custom-asic-with-the-first-open-source-pdk/

https://antmicro.com/blog/2020/06/skywater-open-source-pdk/

 

[Bananasplit_00]

That's pretty cool tbh

[Guest]

I think that’s pretty cool

[williamcll]

130nm is rather behind the times. But I guess all the big corps don't like their precious <10nm manufacturing process running around.

[igormp]

That's really cool, too bad most custom stuff I work on i can't justify going from an FPGA to an actual custom chip.

 

7 hours ago, williamcll said:

130nm is rather behind the times. But I guess all the big corps don't like their precious <10nm manufacturing process running around.

Most microcontrollers are still made in the 130~90nm, with the fancy ones being on 40nm.

[CarlBar]

1 hour ago, igormp said:

Most microcontrollers are still made in the 130~90nm, with the fancy ones being on 40nm.

 

It's still smaller than the node of my first ever desktop processor, (180nm, a 1.6Ghz Pentium 4 era Celeron).

[WelshFruitSnacks]

20 hours ago, williamcll said:

130nm is rather behind the times. But I guess all the big corps don't like their precious <10nm manufacturing process running around.

Well even the 180nm is in production for most major foundries since its a popular node for analog circuits which don't really like worrying about sub-micron effects of smaller nodes. Not everything needs to run 1GHz + which is why its a popular choice for micro controllers some of which might only run at 32KHz possibly for  battery powered sensor controllers. If you want you still can go 1GHz+ with a super deep pipeline like the Pentium III which shows that its good enough for accelerators. 130nm is relativity cheap and has high yields making it good for academic/custom ASIC workloads. As far as I can tell a shuttle at 16mm^2  would be 70K for 100 chips which is about 700$ per chip on a single shuttle which isn't beyond the realm of possibility for a small team to invest in asics (remember a quadro is 5K). Now you would need to pay at least 5 people to design it from the ground up or 3 people to implement an open source design, but < 2K per chip isn't bad. Especially since you can also go and make a full production run of it for super low cost once you know it works.

 

It could also be used by academics so they can save some grant money when doing proof of concept devices. Custom memory controllers for a flash array to handle in memory compute would be an interesting use case.

 

The smallest node used for flash is the 16nm node for Samsung and SK hynix everyone else on flash is still at 20ish. Only top of the line logic cores like fpgas, GPUs (RTX was on 14nm/12nm FinFET) CPU's are prevalent in <20nm.

 

You don't redesign products that work for smaller nodes due to lots of reasons, mostly economic, but also for things like redundant computing which requires low failure rates and/or longevity. Smaller nodes could have possible longevity issues that we just don't know yet.