Science Alert: Self Assembling Circuitry?

WMGroomAK · March 29, 2017

I first found this article on Hexus, but in an article published by MIT and the University of Chicago, researchers are publishing their findings on how to use a modified version of existing lithography microchip circuitry production to create self assembling circuitry smaller than the lithography technique. From the Hexus Article, the process appears to be:

Quote

First a pattern of lines is produced on the chip subscrate using well established lithographic techniques

Secondly, a block copolymer layer is laid down. Made of chain-like molecules of two different polymer materials the layer will predictably segregate itself but remain bonded (this is the beginning of the 'self assembly' stage).

The third step is the adding of a top protective polymer using initiated chemical vapour deposition (iCVD). The top layer constrains the self-assembly of the co-polymers below so they are forced into vertical layers. MIT News describes the layers as resembling a layer cake on its side; I'm thinking 'Signal' toothpaste.

MIT Article: https://news.mit.edu/2017/self-assembly-smaller-microchip-patterns-0327

Hexus Article: http://hexus.net/tech/news/industry/104020-researchers-progress-chip-self-assembly-technique/

The above image is from the Hexus Article with the following quote:

Quote

These scanning electron microscope images show the sequence of fabrication of fine lines by the team's new method. First, an array of lines is produced by a conventional electron beam process (top). The addition of a block copolymer material and a topcoat result in a quadrupling of the number of lines (centre). Then the topcoat is etched away, leaving the new pattern of fine lines exposed (bottom). Credit: MIT News.

Combining this information with the news that Intel is preparing for their 10nm & 10nm+ processes to move forward and in may appear that we can see sub 7nm processes in the near future.