Ram data access

[OuchMyFaceyHole]

My question is a bit specific but here it goes :

Is ram (DDR specifically) accessed in a stripe (data written and accessed to any part of the amount of sticks) or does it fill a stick and move to the next?

[EIijah]

7 minutes ago, Hunter259 said:

My question is a bit specific but here it goes :

Is ram (DDR specifically) accessed in a stripe (data written and accessed to any part of the amount of sticks) or does it fill a stick and move to the next?

I think dual channel stripes it so you can get effectively double the speed, othewise i think it fills by stick number 

[vanished]

This is over my head, but @MageTank

[RedWulf]

I don't believe so, while dual channel and ddr are double the bandwidth and theoretically double the speeds, such are striped raids, its not technically twice the speed per process just per system.

I may be off base here, and I look for a mod to correct and inform me, but I'm fairly sure in ram a particular bit(pun) of data or variable is only in one spot/cell and therefore not striped. The doubled bandwidth is only applicable between multiple processes or threads, leaving the true speed the same. 

The striping in raid is to add speed for a single read or write and larger data, ram is concerned with speed already and handles simpler data, adding striping would require a more advanced memory controller and add latency. So, I'm pretty sure the data of any given task is still stored on the same dimm or cell(s) in a metaphorical solid block and the other cells or dimms are used as needed. 

[MageTank]

7 hours ago, Hunter259 said:

My question is a bit specific but here it goes :

Is ram (DDR specifically) accessed in a stripe (data written and accessed to any part of the amount of sticks) or does it fill a stick and move to the next?

For the most part, RAM is random (hence the name, Random Access Memory). It has a ton of pages to allocate, and is constantly dumping data that is no longer being accessed, and filling back up with different data being accessed. That being said, the IMC often favors pages that are next to other pages, because switching rows costs more time (back to back CAS, or RRSR).

 

Some data structures must remain contiguous though. For example: An array of Nth elements with a base address of 0xYYYYYYYY, each subsequent element must be allocated next to the previous. 

 

I hope this mess of information is somewhat useful to you, as I have never actually been asked this question before. Explaining it is not exactly easy.

[MageTank]

I should add that it's not like Raid0, because Raid0 has a predefined stripe size that it must follow. Ram on the other hand, it's real benefits comes from having more ranks. I don't mean Rank Interleaving either, I mean raw amount of ranks. Ram can only hold one page open per rank, at any given time, being able to open more at the same time is where the extra performance comes from. Rank interleave being the other half, using active ranks while depleted ones are recharging, instead of having to wait. 

 

With multi-channel interleave, its a pool of ranks. Most definitely not like Raid0.  

 

EDIT: There is an exception to this, known as Ganged Mode. Older Dual-Channel used to combine two 64 bit buses into a single 128 bit bus. This is where it would be similar to Raid 0. However, modern Dual Channel no longer does this. I think Wikipedia might have some information on this. https://en.wikipedia.org/wiki/Multi-channel_memory_architecture#Ganged_versus_unganged

 

An easy way to view this, is that it all depends on your IMC. Your IMC dictates absolutely everything about the way your ram works. With each architecture, we see the inner workings of the IMC change, and as a result, the way the data is accessed often changes. The inner latencies change, raw bandwidth is changed, etc. It's why this question is difficult to answer, because it has multiple answers depending on your IMC. 

[OuchMyFaceyHole]

2 hours ago, MageTank said:

I should add that it's not like Raid0, because Raid0 has a predefined stripe size that it must follow. Ram on the other hand, it's real benefits comes from having more ranks. I don't mean Rank Interleaving either, I mean raw amount of ranks. Ram can only hold one page open per rank, at any given time, being able to open more at the same time is where the extra performance comes from. Rank interleave being the other half, using active ranks while depleted ones are recharging, instead of having to wait. 

 

With multi-channel interleave, its a pool of ranks. Most definitely not like Raid0.  

 

EDIT: There is an exception to this, known as Ganged Mode. Older Dual-Channel used to combine two 64 bit buses into a single 128 bit bus. This is where it would be similar to Raid 0. However, modern Dual Channel no longer does this. I think Wikipedia might have some information on this. https://en.wikipedia.org/wiki/Multi-channel_memory_architecture#Ganged_versus_unganged

 

An easy way to view this, is that it all depends on your IMC. Your IMC dictates absolutely everything about the way your ram works. With each architecture, we see the inner workings of the IMC change, and as a result, the way the data is accessed often changes. The inner latencies change, raw bandwidth is changed, etc. It's why this question is difficult to answer, because it has multiple answers depending on your IMC. 

I had figured that different memory controllers would access it differently. Thanks for the explanation.