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This is quite self-explanatory.

How, on a microarchitecture level, do chip designers improve the performance per clock of a processor? Does the logic cycle multiple times per tick? Do they add more function-specific logic to handle certain instructions faster?

Anyone have a good enough understanding of the engineering to give a good answer?

"Do as I say, not as I do."

-Because you actually care if it makes sense.

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33 minutes ago, Dash Lambda said:

Does the logic cycle multiple times per tick?

Yes and sorta.  The amount of instructions used per cycle depends on the software your using.  It's not quite that simple, but that's it in a nutshell

 

33 minutes ago, Dash Lambda said:

Do they add more function-specific logic to handle certain instructions faster?

 You confused me with that one.  Instructions are the logic.

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1 minute ago, done12many2 said:

Yes and sorta.  The amount of instructions used per cycle depends on the software your using.  It's not quite that simply, but that's it in a nutshell

 

 You confused me with that one.  Instructions are the logic.

When I say "logic" I mean the physical circuitry, and when I say "instructions" I mean the actions performed by the circuitry.

Are you saying the instructions are the physical circuitry, or the other way around?

"Do as I say, not as I do."

-Because you actually care if it makes sense.

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Just now, Dash Lambda said:

When I say "logic" I mean the physical circuitry, and when I say "instructions" I mean the actions performed by the circuitry.

Are you saying the instructions are the physical circuitry, or the other way around?

No, that's not what I'm saying.  I started that with "You confused me with that one" so there you have it.  

 

You've got the hamsters spinning the wheel bud.  I like it!

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I think the most notable IPC improvements came from efforts to reduce latency, like moving the memory controller to the CPU.

 

Another way to gradually improve IPC with each generation is to perform more tasks in parallel rather than in series. However, this requires more transistors to perform the same amount of work, thus a larger die and more power. Also I believe the gradual shrinking of the transistors by itself improves IPC. Electricity moves at near lightspeed, the smaller the transistors are, the faster the signal gets to the other side.....

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2 minutes ago, Jonathan Lemmens said:

I think the most notable IPC improvements came from efforts to reduce latency, like moving the memory controller to the CPU.

 

Another way to gradually improve IPC with each generation is to perform more tasks in parallel rather than in series. However, this requires more transistors to perform the same amount of work, thus a larger die and more power. Also I believe the gradual shrinking of the transistors by itself improves IPC. Electricity moves at near lightspeed, the smaller the transistors are, the faster the signal gets to the other side.....

You can't perform most of the low-level tasks in parallel. You usually have to do one logical comparison after another, otherwise you don't have the inputs for the next.

Though, it does seem like decreasing latency makes sense...

"Do as I say, not as I do."

-Because you actually care if it makes sense.

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1 minute ago, Dash Lambda said:

You can't perform most of the low-level tasks in parallel. You usually have to do one logical comparison after another, otherwise you don't have the inputs for the next.

Though, it does seem like decreasing latency makes sense...

Today not everything of course, but usually the most low level tasks are not the ones with a high IPC requirement. Many things can actually be designed to run in parallel, look at GPU computing for example and this trend seems to increase, by the time the quantum CPU will come out, pretty much everything can (and will) run in parallel.

It also depends on the software, when the first dualcore CPU appeared, no software at that time could use both cores simultaneously. 

 

You are right, there are always calculations that depend on the answer of a previous one. 

However these days most computing is done as you mentioned by comparing 2 pieces of data. This used to be done by the same logic gate in 2 clock cycles as the video you mentioned explains. Today it's more common to have 2 identical logic gates in parallel outputting their signal to a third logic gate that then does the comparison, leaving the first two gates free to process the next piece of data. 

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The simple answer is more transistors and improving the architectures design! :D

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Apple A4 - Apple iPod touch (4th generation)
Apple A5 - Apple iPod touch (5th generation)
Apple A9 - Apple iPhone 6s Plus
HiSilicon Kirin 810 (T.S.M.C. 7nm) - Huawei P40 Lite / Huawei nova 7i
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Mediatek MT6737 (T.S.M.C 28nm) - Cherry Mobile Flare S6
Mediatek MT6739 (T.S.M.C 28nm) - my|phone myX8 (blue)
Mediatek MT6739 (T.S.M.C 28nm) - my|phone myX8 (gold)
Mediatek MT6750 (T.S.M.C 28nm) - honor 6C Pro / honor V9 Play
Mediatek MT6765 (T.S.M.C 12nm) - TECNO Pouvoir 3 Plus
Mediatek MT6797D (T.S.M.C 20nm) - my|phone Brown Tab 1
Qualcomm MSM8926 (T.S.M.C. 28nm) - Microsoft Lumia 640 LTE
Qualcomm MSM8974AA (T.S.M.C. 28nm) - Blackberry Passport
Qualcomm SDM710 (Samsung 10nm) - Oppo Realme 3 Pro

 

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