A9 using Victim Cache. Not regular cache.

[AlTech]

 

It appears the A9 chip does not use regular cache And instead is Victim Cache. Wanna know what victim cache is? Funny, you should ask. It's basically where the L3 cache is the same size as L2 cache. In this case it's 6MB which is as much as L3 cache on a quad Core i5 these days 

 

 

 

However it’s also worth mentioning that as Apple is using an inclusive style cache here – where all cache data is replicated at the lower levels to allow for quick eviction at the upper levels – then Apple would have needed to increase the L3 cache size by 2MB in the first place just to offset the larger L2 cache. So the “effective” increase in the L3 cache size won’t be quite as great. Otherwise I’m a bit surprised that Apple has been able to pack in what amounts to 6MB more of SRAM on to A9 versus A8 despite the lack of a full manufacturing node’s increase in transistor density.

 

 

 

As it turns out, 8MB of cache was too good to be true. After a few enlightening discussions with some other individuals, some further testing, and further discussions with Chipworks, both our performance analysis and their die analysis far more strongly point to a 4MB cache. In particular, Chipworks puts the physical size of the TSMC A9 variant’s L3 cache at ~4.5mm

 

 

]2

 

 

, versus ~4.9mm

2 for A8’s L3 cache. Ultimately TSMC’s 16nm FinFET process is built on top of their 20nm process – the metal pitch size as used by Apple is the same with both processes – and this is the limiting factor for the L3 cache SRAM density.

 

That bits supposed to be quote so pls treat it as such. IP board broke quoting

 

 

http://anandtech.com/show/9825/correcting-a9s-l3-cache

 

Opinion - Why you got to do this Apple?

 

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[LAwLz]

Wanna know what victim cache is? Funny, you should ask. It's basically where the L3 cache is the same size as L2 cache. In this case it's 6MB which is as much as L3 cache on a quad Core i5 these days.

Not quite.

A victim cache is a place where things from the L2 cache ends up if things in the L2 cache gets replaced. In the typical setup the L3 cache will have a copy of everything in the L2 cache, which requires the L3 cache to be quite a bit larger than the L2 cache in order to have any purpose at all.

 

 

The A9 has 3MB of L2 cache and 4MB of L3 (victim) cache.

The A9X, for some reason, does not have any L3 cache.

 

 

Apple still has a lot way to go before they can match Intel's 128MB cache on Crystalwell chips though.

[captain cactus]

Not quite.

A victim cache is a place where things from the L2 cache ends up if things in the L2 cache gets replaced. In the typical setup the L3 cache will have a copy of everything in the L2 cache, which requires the L3 cache to be quite a bit larger than the L2 cache in order to have any purpose at all.

 

 

The A9 has 3MB of L2 cache and 4MB of L3 (victim) cache.

The A9X, for some reason, does not have any L3 cache.

 

 

Apple still has a lot way to go before they can match Intel's 128MB cache on Crystalwell chips though.

The A9X doesn't need a L3 cache since since it can talk to memory waaaaay faster. So fast in fact Apple figured L3 cache would actually slow the system down so they opted not to have it.

[suicidalfranco]

The A9X doesn't need a L3 cache since since it can talk to memory waaaaay faster. So fast in fact Apple figured L3 cache would actually slow the system down so they opted not to have it.

[Mew]

Can you make a master thread with all the A9 and A9x threads instead of all these separate small threads or at least try doing that in the future.

[RedRound2]

Well i didn't quite fully understand what is going on but this doesnt change the fact that the A9 is still one of the most powerful chips on a smartphone so i don't see any reason why anyone should complain

[Guest Kloaked]

Opinion - Why you got to do this Apple?

 

Are you trying to make another #VRAMGate with this? They made it work. It's proven in their benchmarks.