(Rumour) - Zen chips have already been tested, met all expectation, no significant bottlenecks

[looncraz]

The math is bulletproof. It all comes down to how honest AMD is being. I take it you never passed any proof-based math course if that's your attitude. You can prove it's bulletproof. As to whether or not the common person understands why a proof is valid...most people here don't understand mathematical induction and proof by contradiction, much less more advanced techniques.

 

We're not getting a 6-core SKU. Zen's been designed in 4-core modules (we have the chip block diagrams straight from AMD confirming this). We're also not getting a single-chip 8-core SKU, only MCMs.

 

There's a concept in modeling, as with software, perhaps you are familiar with it: GIGO.

 

Garbage in, garbage out.

 

You don't have the proper inputs to get the proper outputs.

 

BTW, we will DEFINITELY see 6-core SKUs.  What we may not see are dual-core SKUs (maybe a return of triple-core SKUs?).

 

This is for Opteron and FX CPUs, all with L3, ONLY!

 

Likely Zen Core Configurations:

Zen QCM = Quad Core Module (with common L3 bound to DF bus).

 

Sixteen-Core CPU:

Zen QCM 0: {o0, o1, o2, o3} -> L3

Zen QCM 1: {o0, o1, o2, o3} -> L3

 + DF BUS on MCM +

Zen QCM 0: {o0, o1, o2, o3} -> L3

Zen QCM 1: {o0, o1, o2, o3} -> L3

 

Twelve-Core CPU:

Zen QCM 0: {x0, o1, o2, o3} -> L3

Zen QCM 1: {o0, x1, o2, o3} -> L3

 + DF BUS on MCM +

Zen QCM 0: {o0, o1, o2, x3} -> L3

Zen QCM 1: {o0, x1, o2, o3} -> L3

 

Eight-Core CPU:

Zen QCM 0: {o0, o1, o2, o3} -> L3

Zen QCM 1: {o0, o1, o2, o3} -> L3

 

Six-Core CPU:

Zen QCM 0: {x0, o1, o2, o3} -> L3

Zen QCM 1: {o0, o1, x2, o3} -> L3

 

Quad-Core CPU:

Zen QCM 0: {o0, o1, o2, o3} -> [L3] (possibly less/no L3)

 

Dual-Core CPU: ???  Would have to have bad yields for this...

Zen QCM 0: {x0, o1, o2, x3} -> [L3] (possibly less/no L3)

 

For their APUs, I suspect AMD will stick with quad core, and also with no L3.  They may well have a shared memory buffer for graphics, though.... the will if they want to compete!  May be dedicated for graphics, but with HSA I don't think it would be, unless it was just ill-suited for GPC.

[TechGod]

Yeah, i see what you mean. Though, i thought it was rumored that Zen was supporting quad channel memory as well? Though, it was a rumor (and an old one, at that) so i won't be putting much faith into that being true. 

 

All i know is, too many assumptions are being made on nothing but rumors. None of us can possibly know what Zen will do, until we see it. We have several pieces of the puzzle, but all of the pieces we are missing, are the most important pieces to figure out exactly what we are looking at. Everything discussed in this thread is just guesswork at the moment. Nothing more.

 

I do however, have faith that Zen will succeed IF it can match Haswell. It does not need to match Skylake, because frankly, Skylake is only 5% faster than Haswell in the areas that really count. All other area's can be contributed to DDR4. With that 11% number from before, coming from compression (Raw memory bandwidth). Zen will gain this boon as well, with DDR4. Then again, i am only adding more guesses to an already enigmatic subject. I'll stop talking now.

If Zen gets Haswell level performance, I'll buy it. It'll be my first PC build ever. Waiting for Arctic Islands to drop as well...

[looncraz]

No, I'm saying if the marketers tell the truth, this is the best you could possibly get. It's the same concept of Big-O notation in asymptotic time and memory complexity analysis for algorithms. It tells you the maximal case, but that's not precise enough for a full report, which is why we also have Big Omega for the minimal and Big Theta for the average case, and we even have amortized analysis for a case by case basis analysis. I'm saying the math is bulletproof. How you choose to interpret it and use it is the only variable.

Because 4C dies increase yields and reduce costs, even if there is overhead associated with communication between the modules. It's IBM's very effective strategy instead of using monolithic large dies to control costs and maximize margins per chip. There's no reason to abandon what works if there is no better alternative.

 

I want to see your reasoning for this, because Zen is [0]|[1]|[2]|[3], not [0|1|2|3]... unless AMD really wanted to completely break with everything they've ever done as a company.

 

A quad core module shares L3, and nothing else.  Disabling one core in that module gives the other modules more L3.  If AMD also releases a version with less L3, then they could make even better use of whatever yields they get.

 

With small enough dies, even a poorly yielding process can be profitable.

[TechGod]

I want to see your reasoning for this, because Zen is [0]|[1]|[2]|[3], not [0|1|2|3]... unless AMD really wanted to completely break with everything they've ever done as a company.

 

A quad core module shares L3, and nothing else.  Disabling one core in that module gives the other modules more L3.  If AMD also releases a version with less L3, then they could make even better use of whatever yields they get.

 

With small enough dies, even a poorly yielding process can be profitable.

I don't know as much as about CPU architecture but I just want to see patrick get wrecked ( hate his anti-AMD bias), so by all means, continue:D

[patrickjp93]

I don't know as much as about CPU architecture but I just want to see patrick get wrecked ( hate his anti-AMD bias), so by all means, continue:D

 

I want to see your reasoning for this, because Zen is [0]|[1]|[2]|[3], not [0|1|2|3]... unless AMD really wanted to completely break with everything they've ever done as a company.

 

A quad core module shares L3, and nothing else.  Disabling one core in that module gives the other modules more L3.  If AMD also releases a version with less L3, then they could make even better use of whatever yields they get.

 

With small enough dies, even a poorly yielding process can be profitable.

The quad-core diagrams AMD's been showing off tell the whole story. We're getting MCM designs.

[TechGod]

The quad-core diagrams AMD's been showing off tell the whole story. We're getting MCM designs.

AMD-Zen-Quad-Core-Unit-Block-Diagram.jpg

Link? There was a slide floating around on the internet which turned out to be a highly modified pic of an existing AMD slide. 

[Tomsen]

Sorry for the lateness of my reply, this forum doesn't notify me of comments by email...

 

The INTERNAL ISA is *NOT* known...... [CONTINUED]

I believe it is possible to enable notification by email in your profile settings.

Not only cache latencies, but the caches characteristic in the different query, how cache evictions will go, how will it handle data-locality, and so many other things.

I have been telling him for some time now, that we simply doesn't have the required information available, to actually bulletproof a questimate.

 

 

There's a concept in modeling, as with software, perhaps you are familiar with it: GIGO.

 

Garbage in, garbage out....  [CONTINUED]

That is a nice saying. Should express what I have been trying to tell him.

But it seems like he is convinced he got all the necessary information.

 

I was thinking AMD would go the same setup. Don't really think we will see 2c, who knows.

I personally do believe we will see L3 cache on APUs. Less of an size-issue on 14nm than on 32/28nm.

Maybe some on-chip memory, too? 

 

The quad-core diagrams AMD's been showing off tell the whole story. We're getting MCM designs.

AMD-Zen-Quad-Core-Unit-Block-Diagram.jpg

That diagram doesn't tell much of a story, on how those cores in the module are connected, and how depended it they will be to eachother.

MCM are comming, I'm sure. In what config, we are unsure off.

 

Link? There was a slide floating around on the internet which turned out to be a highly modified pic of an existing AMD slide.

I think said picture is based on the original facked picture (only a single core).

[TechGod]

I believe it is possible to enable notification by email in your profile settings.

Not only cache latencies, but the caches characteristic in the different query, how cache evictions will go, how will it handle data-locality, and so many other things.

I have been telling him for some time now, that we simply doesn't have the required information available, to actually bulletproof a questimate.

That is a nice saying. Should express what I have been trying to tell him.

But it seems like he is convinced he got all the necessary information.

I was thinking AMD would go the same setup. Don't really think we will see 2c, who knows.

I personally do believe we will see L3 cache on APUs. Less of an size-issue on 14nm than on 32/28nm.

Maybe some on-chip memory, too?

That diagram doesn't tell much of a story, on how those cores in the module are connected, and how depended it they will be to eachother.

MCM are comming, I'm sure. In what config, we are unsure off.

I think said picture is based on the original facked picture (only a single core).

So basically, Patrick, as usual, doesn't have any proof for his ridiculous claims?

[Tomsen]

So basically, Patrick, as usual, doesn't have any proof for his ridiculous claims?

Yes.

Doubled checked.

http://juanrga.com/en/the-fake-zen-slides.html

[TechGod]

Yes.

Doubled checked.

http://juanrga.com/en/the-fake-zen-slides.html

He's bashing AMD without reason. I wonder how much Intel pays him?

[Tomsen]

He's bashing AMD without reason. I wonder how much Intel pays him?

He is rather pessimistic regarding AMD.

 

If he were, we would he him going on about him been an intel employee.

This is all his own doing.

[TechGod]

He is rather pessimistic regarding AMD.

If he were, we would he him going on about him been an intel employee.

This is all his own doing.

Back to the topic at hand...utilising more modern instruction sets, splitting the FPU for each core, going to 14nm and I *think* a much better branch prediction algorithm and DDR4 compatibility should definitely put it around Haswell level performance??

[looncraz]

The quad-core diagrams AMD's been showing off tell the whole story. We're getting MCM designs.

AMD-Zen-Quad-Core-Unit-Block-Diagram.jpg

 

Did you pay attention to the words in that there diagram?

 

Of consequence:

 

"Four cores form a unit, share common L3 cache"

"Multiple units can be combined for even greater performance"

 

What this is describing is a quad-core module to replace the existing dual-core modules.  Each core in a module, however, is mostly/fully independent except for the L3 (and probably data fabric bus).

 

What you are saying is the same as claiming Bulldozer CPUs only come in two cores because modules only have two cores.  It's just wrong.

[looncraz]

He's bashing AMD without reason. I wonder how much Intel pays him?

 

juangra is incredibly biased against AMD.

 

He's been spouting off about how 2AGUs isn't enough because you *HAVE* to have a 1:1 AGU ratio.

 

He claims that ADD is 3 uops, with 2 AGU ops.

 

ADD takes three forms:

 

ADD reg, reg  - 1x ALU, 0x AGU

ADD reg, mem - 1x ALU, 1xAGU

ADD mem, reg - 1x ALU, 1xAGU

 

Then, existing AMD architectures don't require that AGU uop much of the time as the address can be determined via an ALU (address offset) or is otherwise known.

 

People even gave him exacting benchmarks which show 1 cycle total average latency for the all ADDs and he doesn't listen, just goes back to ALU:AGU ratios... :wacko:

 

Forum link:

http://semiaccurate.com/forums/showthread.php?p=247242

 

I don't feel like paying $100 to chime in over there

[TechGod]

juangra is incredibly biased against AMD.

 

He's been spouting off about how 2AGUs isn't enough because you *HAVE* to have a 1:1 AGU ratio.

 

He claims that ADD is 3 uops, with 2 AGU ops.

 

ADD takes three forms:

 

ADD reg, reg  - 1x ALU, 0x AGU

ADD reg, mem - 1x ALU, 1xAGU

ADD mem, reg - 1x ALU, 1xAGU

 

Then, existing AMD architectures don't require that AGU uop much of the time as the address can be determined via an ALU (address offset) or is otherwise known.

 

People even gave him exacting benchmarks which show 1 cycle total average latency for the all ADDs and he doesn't listen, just goes back to ALU:AGU ratios... :wacko:

 

Forum link:

http://semiaccurate.com/forums/showthread.php?p=247242

 

I don't feel like paying $100 to chime in over there

Why does that site have to be paid:/

[patrickjp93]

Did you pay attention to the words in that there diagram?

 

Of consequence:

 

"Four cores form a unit, share common L3 cache"

"Multiple units can be combined for even greater performance"

 

What this is describing is a quad-core module to replace the existing dual-core modules.  Each core in a module, however, is mostly/fully independent except for the L3 (and probably data fabric bus).

 

What you are saying is the same as claiming Bulldozer CPUs only come in two cores because modules only have two cores.  It's just wrong.

No, you are twisting what I'm saying. I'm saying more modules will come together, but monolithic dies of 8+cores are highly unlikely except for the HPC APU designs where it makes sense.

 

I'm not wrong at all. You're twisting the meaning of what Ive said and tied it to a straw man with BD that I would have never agreed with.

[Tomsen]

juangra is incredibly biased against AMD.

 

He's been spouting off about how 2AGUs isn't enough because you *HAVE* to have a 1:1 AGU ratio.

 

He claims that ADD is 3 uops, with 2 AGU ops.

 

ADD takes three forms:

 

ADD reg, reg  - 1x ALU, 0x AGU

ADD reg, mem - 1x ALU, 1xAGU

ADD mem, reg - 1x ALU, 1xAGU

 

Then, existing AMD architectures don't require that AGU uop much of the time as the address can be determined via an ALU (address offset) or is otherwise known.

 

People even gave him exacting benchmarks which show 1 cycle total average latency for the all ADDs and he doesn't listen, just goes back to ALU:AGU ratios... :wacko:

 

Forum link:

http://semiaccurate.com/forums/showthread.php?p=247242

 

I don't feel like paying $100 to chime in over there

He really can't get a hold of himself. He really drag discussions out at S|A forums to incredible length.

 

Most and best content is $1000. 

[looncraz]

No, you are twisting what I'm saying. I'm saying more modules will come together, but monolithic dies of 8+cores are highly unlikely except for the HPC APU designs where it makes sense.

 

I'm not wrong at all. You're twisting the meaning of what Ive said and tied it to a straw man with BD that I would have never agreed with.

 

I'm not twisting anything, you're saying that AMD won't be making an eight-core die, when the very evidence you give better supports the idea that it will have an eight core die.

 

CPUs are all about die size and profit.  If AMD were to stick to quad core consumer CPUs for FX CPUs, they may as well just close up shop and offer nothing.  No one will want to buy them unless they have a drastic advantage over Intel.

 

It costs dramatically more to create two dies (albeit not double), and AMD *MUST* have an eight-core die to even think about the server market.  This means they will, without a doubt, have eight core dies on AM4.

 

BTW, you are probably the only person on all of the internet trying to say that AMD will use MCM to achieve an octo-core design.

 

An eight core Zen die will not be much bigger than an eight core Bulldozer die, if at all.

[looncraz]

Also, I found something quite interesting.  I believe this is another Keller design... looks somewhat familiar to me...

 

 

 

Look familiar?

[patrickjp93]

I'm not twisting anything, you're saying that AMD won't be making an eight-core die, when the very evidence you give better supports the idea that it will have an eight core die.

CPUs are all about die size and profit. If AMD were to stick to quad core consumer CPUs for FX CPUs, they may as well just close up shop and offer nothing. No one will want to buy them unless they have a drastic advantage over Intel.

It costs dramatically more to create two dies (albeit not double), and AMD *MUST* have an eight-core die to even think about the server market. This means they will, without a doubt, have eight core dies on AM4.

BTW, you are probably the only person on all of the internet trying to say that AMD will use MCM to achieve an octo-core design.

An eight core Zen die will not be much bigger than an eight core Bulldozer die, if at all.

No, the evidence suggests chips built from 4-core dies. I think you're confusing a die for a complete package. I'm saying 2 4-core dies = 8-core CPU in MCM (Multi-Chip Module) form, similar to the 4 2-core dies that made up the FX series octal core SKUs respectively.

You can build a 32-core flagship from 8 separate dies. It's exactly how their Opterons are built currently too.

No I'm not the only person thinking it. It's a complete waste of resources for the consumer space to be fabbing 8-core dies, decreasing yield, increasing wafers run, etc. For enterprise it makes some sense, but frankly it's pointless outside of the APU designs where MCM designs make the GPU offloading exponentially complex. The experts at Semiwiki believe the same.

[patrickjp93]

Also, I found something quite interesting. I believe this is another Keller design... looks somewhat familiar to me...

Look familiar?

If you're trying to say that looks like the Zen designs in any meaningful way, save yourself the trouble. It doesn't. Everyone's core diagrams put the same items in the same order and have for 8 years. The only variance is the width and count of pipelines or bits to a register or ALU.

[looncraz]

No, the evidence suggests chips built from 4-core dies. I think you're confusing a die for a complete package. I'm saying 2 4-core dies = 8-core CPU in MCM (Multi-Chip Module) form, similar to the 4 2-core dies that made up the FX series octal core SKUs respectively.

You can build a 32-core flagship from 8 separate dies. It's exactly how their Opterons are built currently too.

No I'm not the only person thinking it. It's a complete waste of resources for the consumer space to be fabbing 8-core dies, decreasing yield, increasing wafers run, etc. For enterprise it makes some sense, but frankly it's pointless outside of the APU designs where MCM designs make the GPU offloading exponentially complex. The experts at Semiwiki believe the same.

 

I'm not confusing anything, I know *exactly* what an MCM is, including most of the logistical problems which comes with them - and I'm talking down to the physics of electrons tunneling through the insulator due to thermal stresses and various material properties leading to line impedance changes and cross-talk limiting cross-die communications performance in an MCM configuration.  Though the math often still annoys me :angry: I do it for fun  :wub: 

 

Zen will be using eight-core dies, if not larger, internally arranged in four-core groups, connected via a data fabric bus fast enough to not be a bottleneck across the die (rumored to be 100GB/s, which is plenty for the job, though slow enough to make core-grouping optimizations worthwhile (though that can easily piggy-back on general thread locality without a single line of code changed, so no biggie)).

 

AMD can charge a premium for the six/eight core CPUs if IPC is anywhere near Haswell, which it may well be.  They can create many extra,

very profitable, SKUs:

 

(Assuming they keep the FX name...)

FX-8450 BE - 8 core, SMTFX-8400    - 8 core, no SMTFX-6450 BE - 6 core, SMTFX-6400    - 6 core, no SMTFX-4450 BE - 4 core, SMTFX-4400    - 4 core, no SMT

I kinda expect a new branding of the CPUs, though.

 

They will have a die already with eight cores, for use in servers, enterprise, etc.  The *ONLY* way those CPUs will not find their way to AM4 would be if AMD had so much high-margin demand in the server market that they couldn't possibly keep up - AND they knew about this in advance. This is not likely to occur, and AMD would certainly know better than to expect it - they have burnt too many bridges and will have to re-earn trust before they can regain any traction.

 

They know they also have to earn back some street cred - and the ONLY way to do that is to push into the entry level 2011-v3 territory with a cheaper platform.  Building a whole new platform just to support the tiny HPC market is beyond AMD's grasp at this point in time - and they aren't so stupid as to think that they can just release quad cores and be done with it.

 

*IF* they were to think that, though, they would probably believe they have >= Haswell IPC AND dramatically better SMT than Intel AND equal/greater clock speeds...  That would be a gamble of the greatest proportions considering this is their first SMT CPU, on a new process, with a completely new CPU design...  They would be committing suicide if any ONE of those predictions failed.

 

I have little doubt that AMD will build a quad core die, but they will then push a GPU on it.  This will make the die close to the same size as that of an eight-core die, if not, in  fact, bigger.  Zen dies are rumored to be pretty small B)

[Dabombinable]

I'm not confusing anything, I know *exactly* what an MCM is, including most of the logistical problems which comes with them - and I'm talking down to the physics of electrons tunneling through the insulator due to thermal stresses and various material properties leading to line impedance changes and cross-talk limiting cross-die communications performance in an MCM configuration.  Though the math often still annoys me :angry: I do it for fun  :wub:

 

Zen will be using eight-core dies, if not larger, internally arranged in four-core groups, connected via a data fabric bus fast enough to not be a bottleneck across the die (rumored to be 100GB/s, which is plenty for the job, though slow enough to make core-grouping optimizations worthwhile (though that can easily piggy-back on general thread locality without a single line of code changed, so no biggie)).

 

AMD can charge a premium for the six/eight core CPUs if IPC is anywhere near Haswell, which it may well be.  They can create many extra,

very profitable, SKUs:

 

(Assuming they keep the FX name...)

FX-8450 BE - 8 core, SMTFX-8400    - 8 core, no SMTFX-6450 BE - 6 core, SMTFX-6400    - 6 core, no SMTFX-4450 BE - 4 core, SMTFX-4400    - 4 core, no SMT

I kinda expect a new branding of the CPUs, though.

 

They will have a die already with eight cores, for use in servers, enterprise, etc.  The *ONLY* way those CPUs will not find their way to AM4 would be if AMD had so much high-margin demand in the server market that they couldn't possibly keep up - AND they knew about this in advance. This is not likely to occur, and AMD would certainly know better than to expect it - they have burnt too many bridges and will have to re-earn trust before they can regain any traction.

 

They know they also have to earn back some street cred - and the ONLY way to do that is to push into the entry level 2011-v3 territory with a cheaper platform.  Building a whole new platform just to support the tiny HPC market is beyond AMD's grasp at this point in time - and they aren't so stupid as to think that they can just release quad cores and be done with it.

 

*IF* they were to think that, though, they would probably believe they have >= Haswell IPC AND dramatically better SMT than Intel AND equal/greater clock speeds...  That would be a gamble of the greatest proportions considering this is their first SMT CPU, on a new process, with a completely new CPU design...  They would be committing suicide if any ONE of those predictions failed.

 

I have little doubt that AMD will build a quad core die, but they will then push a GPU on it.  This will make the die close to the same size as that of an eight-core die, if not, in  fact, bigger.  Zen dies are rumored to be pretty small B)

That looks like the road map they'd use for the next FX series if the Phenom II and current FX line are anything to go off.

[patrickjp93]

I'm not confusing anything, I know *exactly* what an MCM is, including most of the logistical problems which comes with them - and I'm talking down to the physics of electrons tunneling through the insulator due to thermal stresses and various material properties leading to line impedance changes and cross-talk limiting cross-die communications performance in an MCM configuration. Though the math often still annoys me :angry: I do it for fun :wub:

Zen will be using eight-core dies, if not larger, internally arranged in four-core groups, connected via a data fabric bus fast enough to not be a bottleneck across the die (rumored to be 100GB/s, which is plenty for the job, though slow enough to make core-grouping optimizations worthwhile (though that can easily piggy-back on general thread locality without a single line of code changed, so no biggie)).

AMD can charge a premium for the six/eight core CPUs if IPC is anywhere near Haswell, which it may well be. They can create many extra,

very profitable, SKUs:

(Assuming they keep the FX name...)

FX-8450 BE - 8 core, SMTFX-8400    - 8 core, no SMTFX-6450 BE - 6 core, SMTFX-6400    - 6 core, no SMTFX-4450 BE - 4 core, SMTFX-4400    - 4 core, no SMT

I kinda expect a new branding of the CPUs, though.

They will have a die already with eight cores, for use in servers, enterprise, etc. The *ONLY* way those CPUs will not find their way to AM4 would be if AMD had so much high-margin demand in the server market that they couldn't possibly keep up - AND they knew about this in advance. This is not likely to occur, and AMD would certainly know better than to expect it - they have burnt too many bridges and will have to re-earn trust before they can regain any traction.

They know they also have to earn back some street cred - and the ONLY way to do that is to push into the entry level 2011-v3 territory with a cheaper platform. Building a whole new platform just to support the tiny HPC market is beyond AMD's grasp at this point in time - and they aren't so stupid as to think that they can just release quad cores and be done with it.

*IF* they were to think that, though, they would probably believe they have >= Haswell IPC AND dramatically better SMT than Intel AND equal/greater clock speeds... That would be a gamble of the greatest proportions considering this is their first SMT CPU, on a new process, with a completely new CPU design... They would be committing suicide if any ONE of those predictions failed.

I have little doubt that AMD will build a quad core die, but they will then push a GPU on it. This will make the die close to the same size as that of an eight-core die, if not, in fact, bigger. Zen dies are rumored to be pretty small B)

Tiny HPC Market? Google, Dell, and Oracle together buy more enterprise CPUs in a quarter than Intel sells consumer grade in a year. Now that enterprise purchase does come with other costs for Intel including support and 24/7 direct line access, but HPC is not small at all. Every big financial institution has its own supercomputer analyzing the financial markets in real time, making investment trades in handfuls of nanoseconds at a time. Every university worth noting I technology has a cluster. The best even have an IBM mainframe, hundreds of nodes on the small end to tens of thousands on the high end, and that's just schools. That's where Intel makes the bulk of its chip sales revenue and profit, not consumer computing.

[looncraz]

Tiny HPC Market? Google, Dell, and Oracle together buy more enterprise CPUs in a quarter than Intel sells consumer grade in a year. Now that enterprise purchase does come with other costs for Intel including support and 24/7 direct line access, but HPC is not small at all. Every big financial institution has its own supercomputer analyzing the financial markets in real time, making investment trades in handfuls of nanoseconds at a time. Every university worth noting I technology has a cluster. The best even have an IBM mainframe, hundreds of nodes on the small end to tens of thousands on the high end, and that's just schools. That's where Intel makes the bulk of its chip sales revenue and profit, not consumer computing.

 

For AMD, it is a tiny market, and will remain as such.  Zen doesn't change that.  Intel is simply too far ahead on that front.  That's what I meant by a tiny market.  The fault for the confusion is mine.