Intel reports flat revenues and lower year-on-year profits for Q3

[Tomsen]

Not true. If their IPC is the same but their instruction sets aren't equialent, you get different results. If the IPC average is the same but the balancing for individual equivalent instructions is different, you end up with different performance.

 

It's not a myth at all. IPC has an absolute limit of 1. Where muops come in and how instructions themselves do multiple things is a separate issue altogether. No instruction can execute in less than 1 cycle. That law is absolute. Since IPC is literally CPI's reciprocal, this is inescapable.

Can we not go into semantics?

 

We are past 1 IPC. Processors today are already fetching, decoding and issuing multiple instructions simultaneously.

2 instructions / 1 cycle = 2 IPC. Some magic ha?

That law most be unwritten?

 

 

not that its faster, ts more flexible

 

And no. Its a phyiscal (well computational law). IPC can not exceed 1. you cant finish every instruction in less then one cycle. Average IPC can, in some cases, and pipelineing combined with superscalar will make it seem as if an instruction finished in less then one cycle, but in reality, it just cant. thats a law.

Physical limitations? Really. What BS are you spouting out now?

You don't need to. You are only looking at one side of the equation. If you can have enough instructions run simultaneously, you don't need to have one to run less that 1 cycle.

[patrickjp93]

Can we not go into semantics?

 

We are past 1 IPC. Processors today are already fetching, decoding and issuing multiple instructions simultaneously.

2 instructions / 1 cycle = 2 IPC. Some magic ha?

That law most be unwritten?

 

 

Physical limitations? Really. What BS are you spouting out now?

You don't need to. You are only looking at one side of the equation. If you can have enough instructions run simultaneously, you don't need to have one to run less that 1 cycle.

No because you can't actually execute multiple instructions at once. That's why the MU-op model was created, to deploy all the pieces and allow layering despite a single entry point. Decoding just allows the Out of Order engine to work its magic and maximize the ILP, only giving the illusion of IPC > 1 It's still a law you cannot escape.

[LukaP]

Can we not go into semantics?

 

We are past 1 IPC. Processors today are already fetching, decoding and issuing multiple instructions simultaneously.

2 instructions / 1 cycle = 2 IPC. Some magic ha?

That law most be unwritten?

 

 

Physical limitations? Really. What BS are you spouting out now?

You don't need to. You are only looking at one side of the equation. If you can have enough instructions run simultaneously, you don't need to have one to run less that 1 cycle.

Clearly you have no idea what youre talking about. Pipleines and superscalar designs only allow the CPU to process more instructions at once, but if you look at all the work it does, it is still n instructions in m cycles where m>n ergo, IPC < 1, they are just compacted together into a pipeline so that each part of the cpu always has work to do...

[BuckGup]

People take this in the wrong way this is actually a very good sign that will happen to all PC things. Intel is at a point now that they are making CPUs so well that people don't need to upgrade every year and pretty soon there will be a cycle that is when everyone upgrades. It will be like every 10 years everyone gets a new PC and then waits. Just wait you will see. MARK MY WORDS!

[Tomsen]

Clearly you have no idea what youre talking about. Pipleines and superscalar designs only allow the CPU to process more instructions at once, but if you look at all the work it does, it is still n instructions in m cycles where m>n ergo, IPC < 1, they are just compacted together into a pipeline so that each part of the cpu always has work to do...

You have some explaination to do. What more work does it do, which cant be done simultaneously while it keep executing?

Looking at your equation.

I already made a very simply example, which I will reuse.

2 Instructions / 1 cycle = 2 IPC.

n instructions in m cycles where n>m ergo, IPC > 1

Instruction pipelining keeps every stage in the pipeline working concurrently.

Superscalar allows multiple instructions to be issued simultaneously.

 

No because you can't actually execute multiple instructions at once. That's why the MU-op model was created, to deploy all the pieces and allow layering despite a single entry point. Decoding just allows the Out of Order engine to work its magic and maximize the ILP, only giving the illusion of IPC > 1 It's still a law you cannot escape.

You're still wrong.

Yes, the unspoken and non-writen law, that somehow everyone else bypass and ignore.

[LukaP]

You have some explaination to do. What more work does it do, which cant be done simultaneously while it keep executing?

Looking at your equation.

I already made a very simply example, which I will reuse.

2 Instructions / 1 cycle = 2 IPC.

n instructions in m cycles where n>m ergo, IPC > 1

Instruction pipelining keeps every stage in the pipeline working concurrently.

Superscalar allows multiple instructions to be issued simultaneously.

 

You're still wrong.

Yes, the unspoken and non-writen law, that somehow everyone else bypass and ignore.

For an instruction to be executed it needs to be completed from fetch to execute. A fetch + a decode + execute (a very simple pipeline example) does not mean 3 instructions in one cycle. it means its working on 3 different instructions in one cycle, but if fetch takes a cycle, and decode takes one, and execute takes one (a very stramlined process) then you will finish each instruction in 1+1+1=3 cycles, meaning .33IPC

 

Its just that your example doesnt work. show me one instruction that goes from fetch to execute in less then one cycle and i will bow down to you as whe god of computing.

 

I do know that, and with superscalar it does appear to be able to go above that limit of one, but the scaling is asymptotic, and also dependent on the sequence of instructions, so that in general (for example in 1s of compute time) the IPC WILL NOT excede 1. i could go dig out the books i have somewhere about this, but i really cant be arsed as this is not that hard to learn about yourself.

 

And since ive explained it 2 times to you now, ill just refer you to STRUCTURED COMPUTER ORGANIZATION, Sixth Edition Pearson Prentice Hall, 2013

[Tomsen]

For an instruction to be executed it needs to be completed from fetch to execute. A fetch + a decode + execute (a very simple pipeline example) does not mean 3 instructions in one cycle. it means its working on 3 different instructions in one cycle, but if fetch takes a cycle, and decode takes one, and execute takes one (a very stramlined process) then you will finish each instruction in 1+1+1=3 cycles, meaning .33IPC

 

Its just that your example doesnt work. show me one instruction that goes from fetch to execute in less then one cycle and i will bow down to you as whe god of computing.

 

I do know that, and with superscalar it does appear to be able to go above that limit of one, but the scaling is asymptotic, and also dependent on the sequence of instructions, so that in general (for example in 1s of compute time) the IPC WILL NOT excede 1. i could go dig out the books i have somewhere about this, but i really cant be arsed as this is not that hard to learn about yourself.

 

And since ive explained it 2 times to you now, ill just refer you to STRUCTURED COMPUTER ORGANIZATION, Sixth Edition Pearson Prentice Hall, 2013

 

Since you somehow manage to ignore what was said, I will go into more details, which cannot as easily be ignored.

Again, a simplified example to demostrate what was said.

 

IF = Instruction Fetch

ID = Instruction decode

EX = Execute

IO = I/O

WB = Write Back

 

Example of how 15 instructions can be executed in 9 cycles.

 

1: IF IF IF

2: ID ID ID IF IF IF

3: EX EX EX ID ID ID IF IF IF

4: IO IO IO EX EX EX ID ID ID IF IF IF

5: WB WB WB IO IO IO EX EX EX ID ID ID IF IF IF

6: WB WB WB IO IO IO EX EX EX ID ID ID

7: WB WB WB IO IO IO EX EX EX

8: WB WB WB IO IO IO

9: WB WB WB

 

15/9 = 1.67 IPC, which exceeds 1.

 

Its just that your example doesnt work. show me one instruction that goes from fetch to execute in less then one cycle and i will bow down to you as whe god of computing.

This is beside my point.

But since the title "god of computing" is on stake, why not?

Intel uop cache, implemented in sandy-bridge, should offer something similar.

 

In Sandy Bridge, there’s now a micro-op cache that caches instructions as they’re decoded. There’s no sophisticated algorithm here, the cache simply grabs instructions as they’re decoded. When SB’s fetch hardware grabs a new instruction it first checks to see if the instruction is in the micro-op cache, if it is then the cache services the rest of the pipeline and the front end is powered down

[cesrai]

Just posting this so I can follow the topic.