AMD Zen (Roadmaps, Quad Core Unit, Block Diagram, 32 Core Opteron)

[Opcode]

They asked for these "fake" slides to be taken down. Even though they traditionally never address rumors.

This only makes them appear more valid in my estimation.

My thought as well as they more than likely didn't want them out before FAD.

 

fake  maybe the timelines are fake but amd moving to a single unified socket has been talked about for a long time now. i cant see AMD waiting till 2017 for Zen hopefully zen drops Q1 2016 that would make me happy... also  the affect of DDR4 on APU's is meh, i want to see HBM Memory on an APU 2Gb of HBM imagine the possibilities

A universal socket is highly expected among most rumors. Deploying a platform has huge advantages if the socket is universal across products. Allowing manufactures to build one solid board for high end (Summit Ridge + OC) and low end (Bristol Ridge). Zen will be launched sometime in 2016 although it's unclear as I guess 1H 2016 is the goal but 2H 2016 is expected. DDR4 on APUs could be a big thing it all depends on how many channels the platform supports. If Bristol Ridge can utilize quad channel DDR4 then their APUs will have a new breath of fire. As Kaveri is severely crippled right now by limited memory bandwidth.

[Eroda]

i wonder how well AMD scaled  dual vs quad channel hopefully they build their memory controller around this.. but i really do hope zen supports ddr4 only new socket/platform they should move to support more newer and modern technologies than intel so feature wise they have an edge on intel to make them more appealing. HBM though that makes me even more excited i cant see it on first gen zen APU's as its still new but by the time 2nd gen is out it would be awesome to have 2/4gb of HBM on their APU man i could only imagine if they could get their CPU to work with HBM also the need for system memory and applicaitons in small form factor devices would be awesome. Im sure ill move to zen i cant see them not having performance my system is so old now even a current vishera cpu is a slight upgrade if zen is 15-20% faster per clock than excavator and they can keep the same high clock rates as vishera it would be nice because even excavator @ the same clocks as current gen would be decent

[TechFan@ic]

My thought as well as they more than likely didn't want them out before FAD.

That's exactly right.

[patrickjp93]

i wonder how well AMD scaled dual vs quad channel hopefully they build their memory controller around this.. but i really do hope zen supports ddr4 only new socket/platform they should move to support more newer and modern technologies than intel so feature wise they have an edge on intel to make them more appealing. HBM though that makes me even more excited i cant see it on first gen zen APU's as its still new but by the time 2nd gen is out it would be awesome to have 2/4gb of HBM on their APU man i could only imagine if they could get their CPU to work with HBM also the need for system memory and applicaitons in small form factor devices would be awesome. Im sure ill move to zen i cant see them not having performance my system is so old now even a current vishera cpu is a slight upgrade if zen is 15-20% faster per clock than excavator and they can keep the same high clock rates as vishera it would be nice because even excavator @ the same clocks as current gen would be decent

AMD lost any hope of that the moment it was confirmed FM3 would target PCIe 3.0 meanwhile Intel's X100 will move up to 4.0 and Z190 (SKL refresh/Cannonlake) will as well.

[Dabombinable]

AMD lost any hope of that the moment it was confirmed FM3 would target PCIe 3.0 meanwhile Intel's X100 will move up to 4.0 and Z190 (SKL refresh/Cannonlake) will as well.

I wonder how many people did a face-desk over that.

[Humbug]

Discussion on Zen from PC perspective

https://youtu.be/Pze0QbfLpD8?t=32m41s

[Eroda]

AMD lost any hope of that the moment it was confirmed FM3 would target PCIe 3.0 meanwhile Intel's X100 will move up to 4.0 and Z190 (SKL refresh/Cannonlake) will as well.

 

 

i must have missed that, link me to source so i can read up on that

[Opcode]

Discussion on Zen from PC perspective

https://youtu.be/Pze0QbfLpD8?t=32m41s

As soon as Josh called a Zen "unit" a "module" I lost interest in what he had to say. The more I watch the more PcPer is shown to know extremely little.

[SeriousDad69]

AMD lost any hope of that the moment it was confirmed FM3 would target PCIe 3.0 meanwhile Intel's X100 will move up to 4.0 and Z190 (SKL refresh/Cannonlake) will as well.

Lol last time I checked PCI-E X16 Gen 1 isn't even slow enough to bottleneck most videocards.

[dalekphalm]

Lol last time I checked PCI-E X16 Gen 1 isn't even slow enough to bottleneck most videocards.

There are certain scenarios where PCIe 4.0 will be beneficial, but certainly not in a normal PC Gaming GPU scenario.

[Glenwing]

Lol last time I checked PCI-E X16 Gen 1 isn't even slow enough to bottleneck most videocards.

 

Not in gaming. In compute acceleration, even PCIe 3.0 x16 shows benefits over x8. Keep in mind everything we've heard about Zen so far (that I'm aware of, I haven't been reading into it) has been about the server/ws processors so that's really what the discussion is about.

[Humbug]

As soon as Josh called a Zen "unit" a "module" I lost interest in what he had to say.

 

He was merely referring to the fact that 4 Zen cores can share the same L3 cache. Think he made that clear...

[Opcode]

AMD lost any hope of that the moment it was confirmed FM3 would target PCIe 3.0 meanwhile Intel's X100 will move up to 4.0 and Z190 (SKL refresh/Cannonlake) will as well.

It's not about generation it's about lane count. If Zen launches with 32 lane support on the CPU then (x16/x16)(x16/x8/x8) would be possible on Gen3 instead of (x16/x8)(x8/x8/x8) that Skylake will likely have on Gen4 (Skylake has been confirmed to have limited lane count). Effectively giving Intel no advantage in this regard. As a single card running in Gen3 @ x16 currently doesn't saturate the interface. We can however already saturate the on-card task controller of the GPU with DirectX 12 draw calls. Which is proof that there is no interface limitation as we currently are effectively topping out the cards capabilities.

 

He was merely referring to the fact that 4 Zen cores can share the same L3 cache. Not modules in the bulldozer sense; think he made that clear.

You do understand this is how Haswell works as well (Zen "unit" and Haswell "unit" are very similar). By his definition Haswell would also be a moduler design. The era of modules is done with as AMD is going back to full cores with Zen. It's just proof that the guy has no clue what he's talking about, almost every 5 seconds he talks I can point out two flaws in his logic. He's on spot about a few things but then he blows it all to hell when he goes on talking about how Zen uses modules.

[cesrai]

Which also use die space for gpus but they are deactivated, it's not any better

And you think Intel doesn't bin CPUs ?

[patrickjp93]

Lol last time I checked PCI-E X16 Gen 1 isn't even slow enough to bottleneck most videocards.

Not the point, and with DX 12 the CPU will be passing information to multiple cards, not just the head card for redistribution. It's the overall value of the platform and the upgrade paths it allows. Anyone interested in heterogeneous computing will also find 4.0 a godsend, as PCIe is a bottleneck for the top-end Teslas right now, which is why IBM's top supercomputers still only use the Tesla K20.

[patrickjp93]

It's not about generation it's about lane count. If Zen launches with 32 lane support on the CPU then (x16/x16)(x16/x8/x8) would be possible on Gen3 instead of (x16/x8)(x8/x8/x8) that Skylake will likely have on Gen4 (Skylake has been confirmed to have limited lane count). Effectively giving Intel no advantage in this regard. As a single card running in Gen3 @ x16 currently doesn't saturate the interface. We can however already saturate the on-card task controller of the GPU with DirectX 12 draw calls. Which is proof that there is no interface limitation as we currently are effectively topping out the cards capabilities.

You do understand this is how Haswell works as well (Zen "unit" and Haswell "unit" are very similar). By his definition Haswell would also be a moduler design. The era of modules is done with as AMD is going back to full cores with Zen. It's just proof that the guy has no clue what he's talking about, almost every 5 seconds he talks I can point out two flaws in his logic. He's on spot about a few things but then he blows it all to hell when he goes on talking about how Zen uses modules.

Most people don't do SLI/XFire above 2 cards. It's less than 1% of gamers. And Z170 provides 20 off the chipset in addition to the 16 from the CPU for networking, raid, PCIe SSDs, sound cards, etc.. And the SKL-E platform will have the 28/40 we're all familiar with.

[patrickjp93]

Lol last time I checked PCI-E X16 Gen 1 isn't even slow enough to bottleneck most videocards.

For anyone doing heterogeneous computing or rendering, PCIe 3.0 x16 was a bottleneck the moment it was released. This is by IBM's supercomputers still only use the Tesla K20 and not the K40 and certainly not the K80. There's no way to keep them fed for full utilization, so you lose efficiency which tends to be a cardinal sin the HPC market.

[SeriousDad69]

For anyone doing heterogeneous computing or rendering, PCIe 3.0 x16 was a bottleneck the moment it was released. This is by IBM's supercomputers still only use the Tesla K20 and not the K40 and certainly not the K80. There's no way to keep them fed for full utilization, so you lose efficiency which tends to be a cardinal sin the HPC market.

Darn I guess if I'm ever getting a super computer or a 10+ thousand dollar workstation I'll have to weigh the pros and cons of PCI-E 3.0 vs PCI-E 4.0.

[patrickjp93]

Darn I guess if I'm ever getting a super computer or a 10+ thousand dollar workstation I'll have to weigh the pros and cons of PCI-E 3.0 vs PCI-E 4.0.

We're entering the era of heterogeneous acceleration of other software too. Don't be a smartass.