Help me tune my DDR5 timings. (Hynix A-Die)

[Od1sseas]

XMP Profile -> 6400Mhz CL32 1.4v

Current OC -> 7200Mhz CL34 1.45v (AIDA64 54.5ns)

 

The only thing i've touched is tREFI. I set it to 100000 (Should i try higher?)

 

[RONOTHAN##]

So, there are a couple things I want to point out first. A die seems to have a ton of variance with the subtimings, so it's not like I can just give you a copy of my subtiming and they'll just work, you will need to do some manual tuning of them to get it to work well. I can give some general guidelines, but you'll have to run your own stress tests and everything. 

 

10 minutes ago, Od1sseas said:

The only thing i've touched is tREFI. I set it to 100000 (Should i try higher?)

I generally set 123456 and then forget about it, there's not that much point going higher performance wise and setting it higher can result in some very weird issues in the long run. I'd probably just leave it at 100000 if it's already set there, but it's up to you. 

 

Anyway, on to the actual timings

• Good kits should be able to do 400 and 300 respectively for tRFC2 and tRFCpb, though 444 and 333 should be a bit more reliable to work.
• The tRRD timings vary a ton between kits, the good ones do 4 7 for s and l respectively, the worse kits do 8 9, so these especially you have to mess around with. 
• the WTR timings aren't real and will be handled by the tertiaries
• tRTP (in the BIOS it should be tRDPRE that you actually set) has a bit of variance as well and tends to scale with frequency. The really good kits at 7200 should do 8, the not-so-good kits might be stuck at 16. 
• tFAW you should just set to 16 and do the tRRDs manually. 
• tCWL has a ton of variance, if you're lucky it'll do half your CAS latency, if you're not lucky you set it to 2 below your CAS latency. This doesn't have a massive performance benefit, but might as well try to get it lower. 
• tCKE usually does 4, but at least on my kit I need to run 12 to get it fully stable and it only fails TM5 1usmus_v3 if tCKE is set too low. It has such a small impact on performance though that just leaving it on auto is not a bad idea. 
• tRDRD varies a bit, at 7200 you can probably get 14-7 stable for sg-dg respectively, if you're not lucky 16-8 rarely doesn't work. The dr-dd timings don't apply in this memory config, either leave them on auto or set them to 1, and this will apply to all the tertiaries.
• tRDWR can sometimes do 19-19 for sg-dg respectively, though for the most part you'll be setting these to 20, and if you're unlucky 22 should always work. 
• tWRRD is what actually sets the tWTR timings, though unfortunately there is a massive amount of variance with these timings. Some kits do 60-44 for sg-dg, others (like mine) struggle to do 70-50. These are more based off your primary timings, so adjusting your primaries will affect these to some degree. 
• tWRWR also varies quite a bit. The really good kits do 9-7 for sg-dg, the not as good kits do 16-8. Your mileage may vary. 
• tWRPRE (the timing that actually sets tWR) is affected by CAS latency a ton. It should be fine at 50, though it might go lower to something like 44, or it might struggle to go low and need to go to 60. This timing also varies quite a bit. 

Basically, they all vary quite a bit. 

[Od1sseas]

16 minutes ago, RONOTHAN## said:

So, there are a couple things I want to point out first. A die seems to have a ton of variance with the subtimings, so it's not like I can just give you a copy of my subtiming and they'll just work, you will need to do some manual tuning of them to get it to work well. I can give some general guidelines, but you'll have to run your own stress tests and everything. 

 

I generally set 123456 and then forget about it, there's not that much point going higher performance wise and setting it higher can result in some very weird issues in the long run. I'd probably just leave it at 100000 if it's already set there, but it's up to you. 

 

Anyway, on to the actual timings

• Good kits should be able to do 400 and 300 respectively for tRFC2 and tRFCpb, though 444 and 333 should be a bit more reliable to work.
• The tRRD timings vary a ton between kits, the good ones do 4 7 for s and l respectively, the worse kits do 8 9, so these especially you have to mess around with. 
• the WTR timings aren't real and will be handled by the tertiaries
• tRTP (in the BIOS it should be tRDPRE that you actually set) has a bit of variance as well and tends to scale with frequency. The really good kits at 7200 should do 8, the not-so-good kits might be stuck at 16. 
• tFAW you should just set to 16 and do the tRRDs manually. 
• tCWL has a ton of variance, if you're lucky it'll do half your CAS latency, if you're not lucky you set it to 2 below your CAS latency. This doesn't have a massive performance benefit, but might as well try to get it lower. 
• tCKE usually does 4, but at least on my kit I need to run 12 to get it fully stable and it only fails TM5 1usmus_v3 if tCKE is set too low. It has such a small impact on performance though that just leaving it on auto is not a bad idea. 
• tRDRD varies a bit, at 7200 you can probably get 14-7 stable for sg-dg respectively, if you're not lucky 16-8 rarely doesn't work. The dr-dd timings don't apply in this memory config, either leave them on auto or set them to 1, and this will apply to all the tertiaries.
• tRDWR can sometimes do 19-19 for sg-dg respectively, though for the most part you'll be setting these to 20, and if you're unlucky 22 should always work. 
• tWRRD is what actually sets the tWTR timings, though unfortunately there is a massive amount of variance with these timings. Some kits do 60-44 for sg-dg, others (like mine) struggle to do 70-50. These are more based off your primary timings, so adjusting your primaries will affect these to some degree. 
• tWRWR also varies quite a bit. The really good kits do 9-7 for sg-dg, the not as good kits do 16-8. Your mileage may vary. 
• tWRPRE (the timing that actually sets tWR) is affected by CAS latency a ton. It should be fine at 50, though it might go lower to something like 44, or it might struggle to go low and need to go to 60. This timing also varies quite a bit. 

Basically, they all vary quite a bit. 

Thanks a lot

[Od1sseas]

22 minutes ago, RONOTHAN## said:

So, there are a couple things I want to point out first. A die seems to have a ton of variance with the subtimings, so it's not like I can just give you a copy of my subtiming and they'll just work, you will need to do some manual tuning of them to get it to work well. I can give some general guidelines, but you'll have to run your own stress tests and everything. 

 

I generally set 123456 and then forget about it, there's not that much point going higher performance wise and setting it higher can result in some very weird issues in the long run. I'd probably just leave it at 100000 if it's already set there, but it's up to you. 

 

Anyway, on to the actual timings

• Good kits should be able to do 400 and 300 respectively for tRFC2 and tRFCpb, though 444 and 333 should be a bit more reliable to work.
• The tRRD timings vary a ton between kits, the good ones do 4 7 for s and l respectively, the worse kits do 8 9, so these especially you have to mess around with. 
• the WTR timings aren't real and will be handled by the tertiaries
• tRTP (in the BIOS it should be tRDPRE that you actually set) has a bit of variance as well and tends to scale with frequency. The really good kits at 7200 should do 8, the not-so-good kits might be stuck at 16. 
• tFAW you should just set to 16 and do the tRRDs manually. 
• tCWL has a ton of variance, if you're lucky it'll do half your CAS latency, if you're not lucky you set it to 2 below your CAS latency. This doesn't have a massive performance benefit, but might as well try to get it lower. 
• tCKE usually does 4, but at least on my kit I need to run 12 to get it fully stable and it only fails TM5 1usmus_v3 if tCKE is set too low. It has such a small impact on performance though that just leaving it on auto is not a bad idea. 
• tRDRD varies a bit, at 7200 you can probably get 14-7 stable for sg-dg respectively, if you're not lucky 16-8 rarely doesn't work. The dr-dd timings don't apply in this memory config, either leave them on auto or set them to 1, and this will apply to all the tertiaries.
• tRDWR can sometimes do 19-19 for sg-dg respectively, though for the most part you'll be setting these to 20, and if you're unlucky 22 should always work. 
• tWRRD is what actually sets the tWTR timings, though unfortunately there is a massive amount of variance with these timings. Some kits do 60-44 for sg-dg, others (like mine) struggle to do 70-50. These are more based off your primary timings, so adjusting your primaries will affect these to some degree. 
• tWRWR also varies quite a bit. The really good kits do 9-7 for sg-dg, the not as good kits do 16-8. Your mileage may vary. 
• tWRPRE (the timing that actually sets tWR) is affected by CAS latency a ton. It should be fine at 50, though it might go lower to something like 44, or it might struggle to go low and need to go to 60. This timing also varies quite a bit. 

Basically, they all vary quite a bit. 

tWRPRE is the tWR timing (that is currently 96)?

[Somerandomtechyboi]

23 minutes ago, RONOTHAN## said:

• tWRRD is what actually sets the tWTR timings, though unfortunately there is a massive amount of variance with these timings. Some kits do 60-44 for sg-dg, others (like mine) struggle to do 70-50. These are more based off your primary timings, so adjusting your primaries will affect these to some degree. 
• tWRPRE (the timing that actually sets tWR) is affected by CAS latency a ton. It should be fine at 50, though it might go lower to something like 44, or it might struggle to go low and need to go to 60. This timing also varies quite a bit. 

So thats what you meant by the primaries not doing much for performance on their own, some subtimings are actually affected by primaries?

 

24 minutes ago, RONOTHAN## said:

tCWL has a ton of variance, if you're lucky it'll do half your CAS latency, if you're not lucky you set it to 2 below your CAS latency. This doesn't have a massive performance benefit, but might as well try to get it lower. 

Tcwl also gobbles volt like cas when you tighten it enough so i wouldnt tighten it to the max, but is tcwl > cl or do they have the same performance impact?

[RONOTHAN##]

Just now, Somerandomtechyboi said:

So thats what you meant by the primaries not doing much for performance on their own, some subtimings are actually affected by primaries?

 

Yeah, on Intel especially the primary timings affect the minimums of the tertiaries. There are times I've gone to raise CAS latency with a fully tuned setup and it fails to train because the subtimings get super unstable. 

 

3 minutes ago, Somerandomtechyboi said:

Tcwl also gobbles volt like cas when you tighten it enough so i wouldnt tighten it to the max, but is tcwl > cl or do they have the same performance impact?

Bit less per clock, but you are able to tighten it a ton if you've got a good kit, so overall performance impact should be about the same. As for the whole "gobbling volts" thing, I prefer the method of just setting your max voltage and lowering the timings from there, so that doesn't really matter. 

 

7 minutes ago, Od1sseas said:

tWRPRE is the tWR timing (that is currently 96)?

Not exactly. tWR is like tWRRD where it's a calculated timing, calculated from tCL, tWRPRE, and tWRPDEN. tWRPDEN is the timing that affects the write delay when entering power down mode, so it generally doesn't actually affect performance in any way, whereas tWRPRE does affect performance. If you want the ASRock Timing Configurator readout to be correct, you want to set tWRPDEN to the same as tWRPRE, but otherwise there's no harm in only changing the one. 

[Od1sseas]

21 hours ago, RONOTHAN## said:

So, there are a couple things I want to point out first. A die seems to have a ton of variance with the subtimings, so it's not like I can just give you a copy of my subtiming and they'll just work, you will need to do some manual tuning of them to get it to work well. I can give some general guidelines, but you'll have to run your own stress tests and everything. 

 

I generally set 123456 and then forget about it, there's not that much point going higher performance wise and setting it higher can result in some very weird issues in the long run. I'd probably just leave it at 100000 if it's already set there, but it's up to you. 

 

Anyway, on to the actual timings

• Good kits should be able to do 400 and 300 respectively for tRFC2 and tRFCpb, though 444 and 333 should be a bit more reliable to work.
• The tRRD timings vary a ton between kits, the good ones do 4 7 for s and l respectively, the worse kits do 8 9, so these especially you have to mess around with. 
• the WTR timings aren't real and will be handled by the tertiaries
• tRTP (in the BIOS it should be tRDPRE that you actually set) has a bit of variance as well and tends to scale with frequency. The really good kits at 7200 should do 8, the not-so-good kits might be stuck at 16. 
• tFAW you should just set to 16 and do the tRRDs manually. 
• tCWL has a ton of variance, if you're lucky it'll do half your CAS latency, if you're not lucky you set it to 2 below your CAS latency. This doesn't have a massive performance benefit, but might as well try to get it lower. 
• tCKE usually does 4, but at least on my kit I need to run 12 to get it fully stable and it only fails TM5 1usmus_v3 if tCKE is set too low. It has such a small impact on performance though that just leaving it on auto is not a bad idea. 
• tRDRD varies a bit, at 7200 you can probably get 14-7 stable for sg-dg respectively, if you're not lucky 16-8 rarely doesn't work. The dr-dd timings don't apply in this memory config, either leave them on auto or set them to 1, and this will apply to all the tertiaries.
• tRDWR can sometimes do 19-19 for sg-dg respectively, though for the most part you'll be setting these to 20, and if you're unlucky 22 should always work. 
• tWRRD is what actually sets the tWTR timings, though unfortunately there is a massive amount of variance with these timings. Some kits do 60-44 for sg-dg, others (like mine) struggle to do 70-50. These are more based off your primary timings, so adjusting your primaries will affect these to some degree. 
• tWRWR also varies quite a bit. The really good kits do 9-7 for sg-dg, the not as good kits do 16-8. Your mileage may vary. 
• tWRPRE (the timing that actually sets tWR) is affected by CAS latency a ton. It should be fine at 50, though it might go lower to something like 44, or it might struggle to go low and need to go to 60. This timing also varies quite a bit. 

Basically, they all vary quite a bit. 

Hey, what's the best app for testing memory stability?

[RONOTHAN##]

2 hours ago, Od1sseas said:

Hey, what's the best app for testing memory stability?

A combination of 2-3 different stress tests. My pick is Y Cruncher VST (this is nearly impossible to pass on 13th gen, it stresses the memory controller and is related to the max frequency you can hit) and TestMem5 1usmus. I run them for 1 and 2 hours respectively, but you ask 3 different people you'll get 3 different answers when it comes to this stuff. 

[Od1sseas]

4 hours ago, RONOTHAN## said:

A combination of 2-3 different stress tests. My pick is Y Cruncher VST (this is nearly impossible to pass on 13th gen, it stresses the memory controller and is related to the max frequency you can hit) and TestMem5 1usmus. I run them for 1 and 2 hours respectively, but you ask 3 different people you'll get 3 different answers when it comes to this stuff. 

Should I overclock the cache? By how much? Will it reduce memory latency? I have a 13600KF (stock/undervolted).

[RONOTHAN##]

18 minutes ago, Od1sseas said:

Should I overclock the cache? By how much? Will it reduce memory latency? I have a 13600KF (stock/undervolted).

Overclocking the cache is a pretty good idea. It helps memory latency a bit, as well as overall system performance. The problem with it is that on 13th gen the cache doesn't really go that far (on on the two chips I've used, they got to 4.8 and 4.9GHz each before becoming very unstable at any voltage, up from the stock 4.5GHz) and it requires an immense amount of core voltage to get stable, so if you're undervolted odds are you minimized the amount of cache voltage necessary, not core voltage necessary. If you're gonna overclock the cache, you've really got to overclock the entire CPU, not undervolt it. 

[Od1sseas]

On 3/4/2023 at 9:48 PM, RONOTHAN## said:

Overclocking the cache is a pretty good idea. It helps memory latency a bit, as well as overall system performance. The problem with it is that on 13th gen the cache doesn't really go that far (on on the two chips I've used, they got to 4.8 and 4.9GHz each before becoming very unstable at any voltage, up from the stock 4.5GHz) and it requires an immense amount of core voltage to get stable, so if you're undervolted odds are you minimized the amount of cache voltage necessary, not core voltage necessary. If you're gonna overclock the cache, you've really got to overclock the entire CPU, not undervolt it. 

Current OC so far. I lowered tRFC and tRFCpb. Didn't mess with the other timings because i got errors so i just gave up and let it at default.

Tried 7600Mhz but i get a blue screen. I tried 1.5 VDD/VDDQ, still blue screen. What could be the issue? Seen people hitting 7600Mhz CL34 with Hynix A-Die

 

[RONOTHAN##]

52 minutes ago, Od1sseas said:

Current OC so far. I lowered tRFC and tRFCpb. Didn't mess with the other timings because i got errors so i just gave up and let it at default.

Tried 7600Mhz but i get a blue screen. I tried 1.5 VDD/VDDQ, still blue screen. What could be the issue? Seen people hitting 7600Mhz CL34 with Hynix A-Die

 

You're probably hitting board and IMC limits. 7200MT/s is about as high end as a 6 layer board can handle. My guess is if you go to launch VST at 7400 it will not work at all. 

 

One thing to know is that every memory voltage on 13th gen sweet spots, which makes overclocking memory on there super annoying. They sweet spot based on the memory speed, timings, kit, BIOS revision, CPU, and board, so they're near impossible to find the sweet spot of all them st the same time that works for finding the appropriate frequency that is fully stable. 

[Od1sseas]

11 minutes ago, RONOTHAN## said:

You're probably hitting board and IMC limits. 7200MT/s is about as high end as a 6 layer board can handle. My guess is if you go to launch VST at 7400 it will not work at all. 

 

One thing to know is that every memory voltage on 13th gen sweet spots, which makes overclocking memory on there super annoying. They sweet spot based on the memory speed, timings, kit, BIOS revision, CPU, and board, so they're near impossible to find the sweet spot of all them st the same time that works for finding the appropriate frequency that is fully stable. 

OK Thanks