IanCutress

Linus used my 5995WX review video at 11:26 so I have no qualms about posting the fact that my video review does have CPU-Rendered Crysis as one of the benchmarks. I've been running CPU-Rendered Crysis on every CPU for a long while. I've created a script to make it work, because it has some really weird config limitations. But here's a link. Timestamp 14:58. 
 
 

Linus used my 5995WX review video at 11:26 so I have no qualms about posting the fact that my video review does have CPU-Rendered Crysis as one of the benchmarks. I've been running CPU-Rendered Crysis on every CPU for a long while. I've created a script to make it work, because it has some really weird config limitations. But here's a link. Timestamp 14:58. 
 
 

Linus used my 5995WX review video at 11:26 so I have no qualms about posting the fact that my video review does have CPU-Rendered Crysis as one of the benchmarks. I've been running CPU-Rendered Crysis on every CPU for a long while. I've created a script to make it work, because it has some really weird config limitations. But here's a link. Timestamp 14:58. 
 
 

Think before you lump us all in to your 'all media is bad' narrative 🙂

Personally I'd say that Cherish balls and/or premiere balls are more suited for roaming legendaries. /s

Initially shocked if true, then skeptical, but then did the leg work and actually went through and found out what it was all about.

Initially shocked if true, then skeptical, but then did the leg work and actually went through and found out what it was all about.

Initially shocked if true, then skeptical, but then did the leg work and actually went through and found out what it was all about.

A wild analyst/influencer has appeared! 
 

 
P.S. Thanks for debunking this "issue" or well non-issue.

Think before you lump us all in to your 'all media is bad' narrative 🙂

Give me a google 🤪
 

Howdy. What's all this then?

Give me a google 🤪
 

Howdy. What's all this then?

Give me a google 🤪
 

Howdy. What's all this then?

Look at who you replied to. Dr. Ian Cutress is a senior editor at Anandtech. Looks like he popped into this thread to show he's noticing the changes being made in a cheeky way.

Howdy. What's all this then?

Howdy. What's all this then?

Howdy. What's all this then?

Just to add this in, as it wasn't included in the video.
 
AMD's ECC for Ryzen is not POR (plan of record), which means it isn't post validated. A system can very well say it's running ECC, and it'll show in the options that ECC is running, but that doesn't actually tell you if ECC is enabled. The only way to truly see if it's enabled is to force a bit-flip and see if it catches it.
 
I responded to Torvalds' thread on RWT with this info at the time.
 
https://www.realworldtech.com/forum/?threadid=198497&curpostid=198715
 
Secondary, DDR5 has ECC per chip, not per module. It's quite a different and important distinction designed mostly for the memory cell reliability than correcting errors. Most DDR5 for consumers will be non-ECC, and ECC variants of DDR5 still require that 9th chip to enable true SECDED support.

Just to add this in, as it wasn't included in the video.
 
AMD's ECC for Ryzen is not POR (plan of record), which means it isn't post validated. A system can very well say it's running ECC, and it'll show in the options that ECC is running, but that doesn't actually tell you if ECC is enabled. The only way to truly see if it's enabled is to force a bit-flip and see if it catches it.
 
I responded to Torvalds' thread on RWT with this info at the time.
 
https://www.realworldtech.com/forum/?threadid=198497&curpostid=198715
 
Secondary, DDR5 has ECC per chip, not per module. It's quite a different and important distinction designed mostly for the memory cell reliability than correcting errors. Most DDR5 for consumers will be non-ECC, and ECC variants of DDR5 still require that 9th chip to enable true SECDED support.

Check the link I posted on how AMD systems potentially say that 'ECC is enabled' but it's just a register check and there's a chance it isn't actually enabled unless you test for it.

Just to add this in, as it wasn't included in the video.
 
AMD's ECC for Ryzen is not POR (plan of record), which means it isn't post validated. A system can very well say it's running ECC, and it'll show in the options that ECC is running, but that doesn't actually tell you if ECC is enabled. The only way to truly see if it's enabled is to force a bit-flip and see if it catches it.
 
I responded to Torvalds' thread on RWT with this info at the time.
 
https://www.realworldtech.com/forum/?threadid=198497&curpostid=198715
 
Secondary, DDR5 has ECC per chip, not per module. It's quite a different and important distinction designed mostly for the memory cell reliability than correcting errors. Most DDR5 for consumers will be non-ECC, and ECC variants of DDR5 still require that 9th chip to enable true SECDED support.

Check the link I posted on how AMD systems potentially say that 'ECC is enabled' but it's just a register check and there's a chance it isn't actually enabled unless you test for it.