Suggestions for learning Verilog

[toobladink]

Hey guys, sorta got in this weird spot. My lecture and lab professors for my logic class are different, and recently we've been getting behind in lecture and it's hurting me in lab. Unfortunately, there are some ideas in lab that aren't in the textbook that we typically go over in lecture, but yesterday I had a lab and had to have someone hold my hand and help me understand what a parameter was in Verilog. I don't think we'll cover that in lecture for another week, maybe week and a half.

 

Anyways, are there any suggestions you can give me about learning strictly the Verilog language? Like what has worked best for you for learning, and why?

[toobladink]

Shameless bump, would really appreciate suggestions to learn Verilog as it isn't covered much in my lecture section but it's an expectation for my lab!