VHDL Pros, Anyone?

mackncheesiest · May 26, 2015

I figure it's a bit of a stretch since this is primarily a CS-oriented forum, but is there anyone here with experience in VHDL? I've got a decent amount of experience in Verilog, and I was trying to make the switch over to VHDL since the place I'll be working with over the summer has an existing codebase built with it.

Anyway, I was working through some small projects trying to get the hang of things, and I've currently hit a bit of a brick wall in my current design with some kind of conflict happening between what I think is a STD_LOGIC or STD_LOGIC_VECTOR data type conversion error.

Right now, it's basically a simple clock divider hooked up to a controller for a multi-digit seven segment display (the clock div's slowing the clock down to a proper refresh rate for the 8-digit display), and it's giving me a synthesis error of

module 'sevensegdecoder' declared at 'projectPath/sevenSegDisp/sevenSegDisp.srcs/sources_1/new/sevenSegDecoder.vhd:34' does not have matching formal port for component port 'leds' ["projectPath/sevenSegDisp/sevenSegDisp.srcs/sources_1/new/FixedPointAdder_top.vhd":65]

And internet searching hasn't quite turned up anything yet. Attached below is my full top module where everything is going to hell, and if anyone has any idea what might be happening here, that'd be cool.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity MyModule_top is    Port ( clk : in STD_LOGIC;           dpad : in STD_LOGIC_VECTOR (4 downto 0);           myleds : out STD_LOGIC_VECTOR (6 downto 0);           sevSegEn : out STD_LOGIC_VECTOR (7 downto 0));end myModule_top;architecture Behavioral of MyModule_top is    signal slowClk : STD_LOGIC;     signal dedpad : STD_LOGIC_VECTOR (4 downto 0);        component sevenSegDecoder is        port ( clk : in STD_LOGIC;                dpad : in STD_LOGIC_VECTOR (4 downto 0);               leds : out STD_LOGIC_VECTOR (6 downto 0);                sevenSegEn : out STD_LOGIC_VECTOR (7 downto 0));    end component;        component Clock_Div is        generic ( divVal : integer );        port ( clk : in STD_LOGIC; divClk : out STD_LOGIC);    end component;        component dPadDebouncer is        Port ( dpad_in : in STD_LOGIC_VECTOR (4 downto 0);               clk : in STD_LOGIC;               dpad_out : out STD_LOGIC_VECTOR (4 downto 0));    end component;begin    clkDiv : Clock_Div generic map (divVal => 12500) port map (clk => clk, divClk => slowClk);--    dbouce : dPadDebouncer port map (dpad_in => dpad, clk => clk, dpad_out => dedpad);     sevSeg : sevenSegDecoder port map (clk => slowClk, dpad => dpad, leds => myleds, sevenSegEn => sevSegEn);end Behavioral;