LPDDR5 6400

[paddy-stone]

Hey, just a quick question/observation.

 

I noticed that my RAM in HWINFO64 shows 786.5Mhz under the max column. When I looked in CPU-z for confirmation, I saw that it said FSB/uncore? was 1:8, so took that to mean that the memory clock frequency FSB should be x8 to get the approx 6400Mhz that I was looking for?

 

I just got a 6800U mini-pc to replace those times when I'm mostly doing not much but browsing and listening to music etc... but still a decent enough performance for most stuff. I might even try dual-booting with OMV to see what the performance is like as a NAS.

[AndreiArgeanu]

DDR is Double data rate so the speed should be twice what is being read out. my FSB:DRAM is 1:16 and I'm running 3200mhz memory, there's no way it's running 256000mhz. This is what CPU-Z and HWINFO64 is showing for me with DDR4. Can you post some screenshots of yours as well.

 

[Alex Atkin UK]

1 hour ago, paddy-stone said:

Hey, just a quick question/observation.

 

I noticed that my RAM in HWINFO64 shows 786.5Mhz under the max column. When I looked in CPU-z for confirmation, I saw that it said FSB/uncore? was 1:8, so took that to mean that the memory clock frequency FSB should be x8 to get the approx 6400Mhz that I was looking for?

No, that merely is saying the FSB is running at 1/8th the speed of the DRAM.

[paddy-stone]

Ahh OK, that's why I wanted to check... my ram is running way slow then. I've also checked in bios and it's reporting that it's running at 6400, so not sure what's going on.

 

 

 

[paddy-stone]

I found this info:

 

New Scalable Clocking Architecture for Easier Timing Closure

The C/A CK has typically run at the same frequency as the data-strobes (DQS) in all prior LPDDR standards, up to LPDDR4/4X. Such a clocking scheme puts enormous pressure on both the DRAM C/A lanes and the SoC timing convergence, since the CK is the reference for C/A lanes on the memory channel and the memory controller in the SoC typically runs at half the CK frequency at the DDR PHY Interface in the DFI 1:2 ratio mode. For example, for an LPDDR4/4X speed of 4267 Mbps, the CK and DQS run at 2133 MHz, and the C/A has a data-rate of 2133 Mbps and controller clock runs at 1066 MHz.

Such a clocking scheme is not scalable at LPDDR5 speeds. Thus, LPDDR5 adopts a new clocking scheme, where CK runs at one fourth the data-strobe frequency at speeds higher than 3200 Mbps, and at half the data-strobe frequency at speeds under 3200 Mbps. Hence, even at 6400 Mbps, this clocking scheme requires CK to operate only at 800 MHz. This allows C/A to run slower (at 1600 Mbps, since C/A can transition at both rising and falling edges of CK rate (for example: DDR type) in LPDDR5) and hence greatly improves the margins on the C/A lanes. Similarly, a slower CK enables the SoC to not only close timing more efficiently, but also provides a higher performance, since the controller can now work at 800 MHz in DFI 1:1 ratio. Additionally, LPDDR5 does not support the traditional bi-directional data-strobe architecture, and instead introduces two uni-directional data-strobes: Write clock (WCK) for Writes and an optional Read clock (RDQS) for Reads. The system can choose to operate either strobe-less or with a single-ended strobe for Reads at lower speeds and save power, although a differential strobe (RDQS/RDQS#) becomes necessary for higher speeds.        

 

source: https://www.synopsys.com/designware-ip/technical-bulletin/key-features-about-lpddr5.html

 

So in essence even though it's reporting 800Mhz, this is normal