Help from smart electrical/computer engineer people.

[wasab]

I am taking a course in system architecture and right now cramming for the midterm. 

Is anyone able to work me through these first two problems? I am to implement an ALU(arithmetic logic unit). The course is using MIPS CPU to teach computer architecture if that helps in any way.

it is not homework, just practice. I wish to see a tutorial on the first two and then work out the rest on my own. 

[mr moose]

 

 

This may help. 

 

From the question it sounds like you just need to be able to build the circuit using logic gates to enable the ALU to carry out the required function.

 

[wasab]

7 hours ago, mr moose said:

 

 

This may help. 

 

From the question it sounds like you just need to be able to build the circuit using logic gates to enable the ALU to carry out the required function.

 

Shows like these are quick introductions for laymans similar to a documentary. They are made for those not studying in the field and just curious. I already know what adder and ALU does. 

 

Manually building one with logic gates involve more than just chaining together adders.  Quite a bit of Boolean algebra and math is involve which this video has come nowhere close to explaining. 

[Dash Lambda]

Looking at question #1:

• -B: This depends on your representation. You're most likely using two's complement, for which this operation consists of performing a bitwise NOT on B then adding 1.
• A-B: You negate B then add it to A.
• A+B: This consists of just adders.
• A XOR B: This one also just consists of adders. A 1-bit adder is really just an XOR gate with carry bits, so you just disconnect the carries.

Now, there are two ways you could build this ALU: Build a dedicated circuit for each operation then MUX all the outputs together, or condense it all into one block of adders and MUX the inputs. The first way makes me angry, so let's see how you can rearrange things in the second one...

• Saying -B is the same as saying 0-B, and XOR is adding without the carries, so you can rewrite your operations as {0-B, A-B, A+B, A+B (without carry)}. All four can be done with a single block of adders! You just need to change the inputs for the first three and disable carry for the last one.
• The "A" input is 0 for the first one and A for the other three. So all you need to do is MUX A and a 0 signal together. The MUX chooses 0 for 00 and A for 01, 10, 11, so you can use an OR gate for the select bit.
• The "B" input is -B for 00, 01 and B for 10, 11. So you can MUX together a B and negated B, select bit is the high-order control bit, and when it's negated B you add a carry-in on the top adder (which'll be A+(NOT B)+1 = A-B).
• At this point, we've got -B, A-B, and A+B. We just need XOR, which is, as I said, just A+B with the carry disabled. Both 10 and 11 are A+B at the moment, so all you have to do is stick an AND gate between the two adders and a NAND gate on the control input, then you've got XOR!
• The Result and Carry_out outputs are straightforward, and for the Zero output just NOR the result bits together.

Here's what that looks like in Logisim. I used 2-bit wide inputs, MUX's, and a 2-bit output for Result to clean it up:

 

As for #2 (I'll be less explicit here):

• A+B: Same as before.
• A-B: Same as before.
• B-A: This'll just add some MUXing.
• A AND B: The carry out on an adder without a carry in is the AND of its inputs.

Implementation:

• You're MUXing on the output now, too, since you have one output coming from the adder sums and one coming from the carry outs.
• You're connecting/disconnecting both carry ins now.
• For the three operations where the first carry in is connected, the carry bit is the NOR of the control bits.
• Both A and B each have a MUX to NOT them, and the select bit for each one should be the AND of one control bit and the signal that connects the carries.

[wasab]

5 hours ago, Dash Lambda said:

Looking at question #1:

• -B: This depends on your representation. You're most likely using two's complement, for which this operation consists of performing a bitwise NOT on B then adding 1.
• A-B: You negate B then add it to A.
• A+B: This consists of just adders.
• A XOR B: This one also just consists of adders. A 1-bit adder is really just an XOR gate with carry bits, so you just disconnect the carries.

Now, there are two ways you could build this ALU: Build a dedicated circuit for each operation then MUX all the outputs together, or condense it all into one block of adders and MUX the inputs. The first way makes me angry, so let's see how you can rearrange things in the second one...

• Saying -B is the same as saying 0-B, and XOR is adding without the carries, so you can rewrite your operations as {0-B, A-B, A+B, A+B (without carry)}. All four can be done with a single block of adders! You just need to change the inputs for the first three and disable carry for the last one.
• The "A" input is 0 for the first one and A for the other. So all you need to do is MUX A and a 0 signal together. The MUX chooses 0 for 00 and A for 01, 10, 11, so you can use an OR gate for the select bit.
• The "B" input is -B for 00, 01 and B for 10, 11. So you can MUX together a B and negated B, select bit is the high-order control bit, and when it's negated B you add a carry-in on the top adder (which'll be A+(NOT B)+1 = A-B).
• At this point, we've got -B, A-B, and A+B. We just need XOR, which is, as I said, just A+B with the carry disabled. Both 10 and 11 are A+B at the moment, so all you have to do is stick an AND gate between the two adders and a NAND gate on the control input, then you've got XOR!
• The Result and Carry_out outputs are straightforward, and for the Zero output just NOR the result bits together.

Here's what that looks like in Logisim. I used 2-bit wide inputs, MUX's, and a 2-bit output for Result to clean it up:

 

As for #2 (I'll be less explicit here):

• A+B: Same as before.
• A-B: Same as before.
• B-A: This'll just add some MUXing.
• A AND B: The carry out on an adder without a carry in is the AND of its inputs.

Implementation:

• You're MUXing on the output now, too, since you have one output coming from the adder sums and one coming from the carry outs.
• You're connecting/disconnecting both carry ins now.
• For the three operations where the first carry in is connected, the carry bit is the NOR of the control bits.
• Both A and B each have a MUX to NOT them, and the select bit for each one should be the AND of one control bit and the signal that connects the carries.

Awesome. Now I just need a couple minutes to understand this...