vhdl VHDL testbench

[hi_im_alex]

Hi guys, I need to test an adder in vhdl, the main thing is that I have to select the most important examples, given that it is a 64 bit adder I can't make 2⁶⁴  cases. Which are the inputs with higher result error possibility? 

[straight_stewie]

5 hours ago, hi_im_alex said:

Hi guys, I need to test an adder in vhdl, the main thing is that I have to select the most important examples, given that it is a 64 bit adder I can't make 2⁶⁴  cases. Which are the inputs with higher result error possibility?  

What you're looking for is groups of tests that are indicative of the whole. Some examples for addition might be:

• Edge cases: 0 + 0, $FFFFFFFF + $00000001
• Normal cases: Anything between the above that will not produce an overflow, carry, or half carry
• Various cases that will produce an overflow, carry, or half carry.
• Any other logic errors or conditions that your adder has been designed to deal with or fault on.
• If you also implement any signed arithmetic, the same as above for that.
• If you also implement subtraction, the same as above for that.
• Any timing constraints that are part of the design requirements.