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Hi all, This topic is related to different kinds of hardware. My company develops FPGA acceleration boards. These boards are connected via PCIe and are used to accelerate different applications: from Neural networks and Network to Video Encoding. Our technology is new and has performance advantage over existing solutions. We consider to make hardware encoder solution. I don't have a lot of experience in this so I need to understand current situation and niches we can suit: from consumer solutions to business. My experience is only several streams with OBS. I'd like to discuss Nvidia encoding, devices like Elgato and analogues, AWS Elemental Link, what are the parameters that affect the price and use cases (church/school/business_conference/gaming/event_multi_cameras streaming). Besides such on-premise solutions there might be server solutions (as PCIe boards) to encode many sources simultaneously at CDN side. We have possibility to use more powerful FPGA chips to suit required level of performance. Our boards are accelerators and they accelerate snippets of code where execution might be highly parallelized, the other part of code is still running on CPU. So we depend on PC and board has to be connected to device with CPU (PC/Laptop). So one of the solutions is small device connected to Laptop via Thunderbolt, another is just usual PCIe board for PC. For server it's also PCIe board. Supported codecs are defined only by software and different formats can have support over time. Considered formats are from AV1/HEVC to h.264 with 4k60 and lower quality. We're looking for encoding software partners to adapt to our boards. Regarding Nvidia I've seen that they have 2 encoders per card. Does this mean that 2 medias could be encoded in parallel? Do gamers need 2nd GPU or auxiliary hardware to stream with high quality? Are Elgato like devices still relevant? The topic is quite wide and I appreciate everyone's opinion. DM me if you wish to talk

I have an ALU design and it is verified to be working with testbench in modelsim. I am now trying to get textual output to the HD44780U LCD display. But after a week I am still at the same spot. I really need help with this project. I just want to learn how to display text to the lcd screen every state of the ALU. Should each state output have it's own module? Edit: Do I need to provide more information? I want to learn how to display text but I have no idea how to do it. I have tried reading the manual for HD44780U but I wasn't able to do much. ALU_SV.qpf ALU_SV.v ALU_SV_TB.v LCD_Display.v

https://www.nextplatform.com/2017/03/21/can-fpgas-beat-gpus-accelerating-next-generation-deep-learning/ Warning, large images. So it seems the battle in supercomputers may shift away from GPGPUs to more efficient processors, even if customizing them on the fly is currently a bit painful. All in all it looks like exciting times ahead, and the race to Exascale will be a tight one between AMD, Nvidia, Intel, and Xilinx. It should be noted that the Stratix 10 is nowhere near Intel's max die size tolerances for 14nm, and in fact it's only 70% the size, meaning there's ~40% more performance to squeeze in on the same node with no architecture change. If only I could afford one

I was wondering when you test new processors, could you test performance running Xilinx tools. How long to synthesize a design? How long to place and route a design? This is a business application where faster CPUs can be beneficial, more cores not necessarily.

Hello everyone, I am in the process of building a workstation for image acquisition. I will try to simplify the information for general use, rather than talking extensively about research(: Currently, I use four highspeed PCO edge 5.5 cameras, which are connected to 2 workstation PC’s. My goal is to use one computer to run all the cameras instead of two. A company a few years ago offered two build two PC’s for me, one for two cameras and one for four cameras. (The information is given below). This was in 2016 so I am hoping that mores law is working in my favor. Here are the two build configurations that I am using as reference for the new build. I have left all the details, even though my major interest is selecting the proper Motherboard and CPU’s since those are the most important for this application. There is a bit of fluff (networking stuff) that I don't really need, kinda seems like overkill idk. links: ttps://ark.intel.com/content/www/us/en/ark/products/77781/intel-core-i7-4820k-processor-10m-cache-up-to-3-90-ghz.html https://www.supermicro.com/products/motherboard/Xeon/C600/X9SRA.cfm https://ark.intel.com/content/www/us/en/ark/products/64592/intel-xeon-processor-e5-2603-10m-cache-1-80-ghz-6-40-gt-s-intel-qpi.html https://www.supermicro.com/products/motherboard/Xeon/C600/X9DRX_-F.cfm BACKGROUND: The highspeed cameras require “Frame Grabber” Cards that connect via the PCI ports. I will be using four cards one for each camera. Therefore, at minimum, I will need 5 PCI ports (GPU). Frame Grabber Cards: https://silicon.software/product/microenable-iv-vd4-cl/ -Quick Spec’s microEnable IV VD4-CL focuses on fast image processing with all Camera Link cameras and enables with DMA900 technology and VisualApplets advanced customized applications with the robust industrial Machine Vision standard. • All formats of Camera Link standard including non-Standard formats** • BayerHQe Quality (5x5) • Image Enhancement by On-Board Noise Filter • Shading Correction (Offset and Gain) • DMA900 / up to 900 MB/s PCIe Data bandwidth (PCIe x4) • Camera Simulator • Broad support of Third-party software interfaces • Versatile application and industry usage • Easy programmable Vision processor for individual realtime functionality • Robust and industrial FPGA Technology PIC: How much data is generated? I currently can only record 10 seconds worth of data, on average ~2.4 Gb/s, so ~24 GB’s of data is generated per trial. It all stored on ram before it is written to disk. Let's assume the maximum which is 900 MB/s x 4 = 3.6 GB/s . Questions Do I still need a dual CPU board? Or will a modern-day single CPU suffice? Which motherboard is “Best”? Component recommendations? How can I best determine which components are applicable for the system? I would like to make the system KINDA portable since I will be moving between labs. Since I will have to get this approved, I would like to have a budget configuration and a moderate configuration. The budget build being the minimum configuration to just connect the four cameras. My main goal is to use one computer to connect the four cameras too since using two computers isn't fun. I can run some tests to see the load on the current workstations if that will help. ANY HELP IS MUCH APPRECIATED! Just need a little guidance

Thanks to SiFive for sponsoring this video! Check our their core designer at https://www.sifive.com/core-designer

Intel has recently started shipping their xeon scalable gold 6138P with an on-package arria 10 gx1150 FPGA ( 1.15M logic elements ) . The cpu is the same as the regular Xeon gold 6138 , with 20 cores and 40 threads ,based on the (revised) skylake architecture and is dual socket capable. The whole on-package FPGA idea has been floating around for quite some time now ( intel demoed a broadwell chip featuring the tech a while back ). It was actually one of the main drivers of intel's EMIB and omnipath interconnect technologies . source : https://www.anandtech.com/show/12773/intel-shows-xeon-scalable-gold-6138p-with-integrated-fpga-shipping-to-vendors

As I've said before: Intel is not built of fools. Intel wants more business, and as Kirzanich says here, if it wins Intel the business, it's willing to make ARM cores for as long as needed (prefaced by saying Intel's average product lifetime is 12 years). Prediction: in 5 years, the mobile world will still run ARM, but Intel will be a player to be reckoned with at last. Sorry if this seems like this should have been combined with my FPGA post, but I feel these are two very big pieces of news that deserve their own discussions. "We have no plans, none! I don't care what you hear, what the competition says, or anything else. There's no plan to yank ARM out and stick in IA and make you guys change all your programming models, absolutely none. I do believe there will be some additional products in the future, and I want you guys to take advantage... Virtualization, multiple operating systems on an FPGA per core, ... "

http://www.pcper.com/news/Processors/Intel-Launches-Stratix-10-FPGA-ARM-CPU-and-HBM2 Shipping is said to begin by the end of the year (Kirzanich, IDF 2016) Sampling has begun. Stratix 10 SOC: 4 Partly customized ARM A53 cores 4 stacks of HBM2 at 1TB/s in bandwidth (8 or 16GB total not given) Intel/Altera FPGA 5.5 Million Logic Elements HyperFlex Optimization for registers and critical paths 5x the logic density vs. Altera's previous products 70% less power Onboard ECC and end to end data encryption/integrity checks 10TFlops Single Precision DSP (can do 5 DP or can do a mix b/c it's an FPGA) 80 gigaflops per watt or 125W for the whole enchilada (misprint in the article would mean 125Gigawatts, so obviously it's flipped). Dimensions not yet provided, but we do have a graphic. It's way smaller than Fiji. I would be very angry if I was IBM or Xilinx right now. This is one serious piece of silicon. For comparison, Xilinx's top of the line FPGA today: https://www.xilinx.com/products/silicon-devices/fpga/virtex-ultrascale-plus.html 3.78 million logic elements (Intel has a 45.5% advantage here) Uses (if I'm reading this correctly) quad-channel DDR4 2666 for main memory, but has a total internal fabric bandwidth of 1.05TB/s and nearly 1Tb of ethernet fabric (It's built for high-speed derivatives trading, which is also why it costs $40,000 to buy ONE of them. It's also used for radar/sonar and other signal processing, so there are many other performance metrics to look at, but that's the gist of it. Update: 80GFlops/Watt confirmed by Altera representative. https://youtu.be/zI_thFZQzgc?t=2m9s

So at school I have the lecture "embeded hardware and software". For 4 month we got an FPGA board with some periphery to do your howework. Today I set up an SoPC (System on Programmable Chip) and it includs a CPU made of logic gates and registers. Have a look (use the PDF to zoom in all the way): That's how a simple CPU looks like. It is made of approximate 2000 logic gates and 1300 registers. To be honsted I used an IP block provided by Altera and didn't build it from scratch. I could, but it will take me several weeks working full time on it. CPU.pdf

From Altera Not to familiar with this FPGA SOC stuff so don't know what to comment on. Still, it's nice to see technology going forward. http://wccftech.com/intel-altera-offering-hbm2-fpga-sip-stratix-10/

source: http://newsroom.intel.com/community/intel_newsroom/blog/2015/12/28/intel-completes-acquisition-of-altera back in June 2015, Intel and Altera announced an agreement under which Intel would acquire Altera for 54$ / share, a transaction valued at over 16.7 bilion USD - yesterday, December 28, that transaction closed The combination is expected to enable new classes of products that meet customer needs in the data center and Internet of Things (IoT) market segments. Intel plans to offer Altera’s FPGA products with Intel Xeon processors as highly customized, integrated products. --- Altera, founded in 1983, was the industry 1st to deliver a reprogrammable logic device (in 1984) – the EP300 further reading: https://www.altera.com/solutions/technology/system-design/articles/_2013/in-the-beginning.html --- what is a FPGA? FPGA stands for Field Programmable Gate Array - an integrated circuit (IC) designed to be configured by a customer or a designer after manufacturing

I figure it's a bit of a stretch since this is primarily a CS-oriented forum, but is there anyone here with experience in VHDL? I've got a decent amount of experience in Verilog, and I was trying to make the switch over to VHDL since the place I'll be working with over the summer has an existing codebase built with it. Anyway, I was working through some small projects trying to get the hang of things, and I've currently hit a bit of a brick wall in my current design with some kind of conflict happening between what I think is a STD_LOGIC or STD_LOGIC_VECTOR data type conversion error. Right now, it's basically a simple clock divider hooked up to a controller for a multi-digit seven segment display (the clock div's slowing the clock down to a proper refresh rate for the 8-digit display), and it's giving me a synthesis error of module 'sevensegdecoder' declared at 'projectPath/sevenSegDisp/sevenSegDisp.srcs/sources_1/new/sevenSegDecoder.vhd:34' does not have matching formal port for component port 'leds' ["projectPath/sevenSegDisp/sevenSegDisp.srcs/sources_1/new/FixedPointAdder_top.vhd":65] And internet searching hasn't quite turned up anything yet. Attached below is my full top module where everything is going to hell, and if anyone has any idea what might be happening here, that'd be cool. library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity MyModule_top is Port ( clk : in STD_LOGIC; dpad : in STD_LOGIC_VECTOR (4 downto 0); myleds : out STD_LOGIC_VECTOR (6 downto 0); sevSegEn : out STD_LOGIC_VECTOR (7 downto 0));end myModule_top;architecture Behavioral of MyModule_top is signal slowClk : STD_LOGIC; signal dedpad : STD_LOGIC_VECTOR (4 downto 0); component sevenSegDecoder is port ( clk : in STD_LOGIC; dpad : in STD_LOGIC_VECTOR (4 downto 0); leds : out STD_LOGIC_VECTOR (6 downto 0); sevenSegEn : out STD_LOGIC_VECTOR (7 downto 0)); end component; component Clock_Div is generic ( divVal : integer ); port ( clk : in STD_LOGIC; divClk : out STD_LOGIC); end component; component dPadDebouncer is Port ( dpad_in : in STD_LOGIC_VECTOR (4 downto 0); clk : in STD_LOGIC; dpad_out : out STD_LOGIC_VECTOR (4 downto 0)); end component;begin clkDiv : Clock_Div generic map (divVal => 12500) port map (clk => clk, divClk => slowClk);-- dbouce : dPadDebouncer port map (dpad_in => dpad, clk => clk, dpad_out => dedpad); sevSeg : sevenSegDecoder port map (clk => slowClk, dpad => dpad, leds => myleds, sevenSegEn => sevSegEn);end Behavioral;

http://www.kitguru.net/components/cpu/anton-shilov/intel-first-full-custom-xeon-cpus-are-due-next-year/ For a long time now Intel has combined Altera FPGAs onto customized flavors of its top SKUs for the likes of Microsoft and Amazon in order to provide as much flexibility for acceleration of mission-critical algorithms as possible, but in the financial sector where microseconds and even nanoseconds matter to make lightning-fast trades based on the outcomes of those algorithms, IBM's Power and Oracle's SPARC lend themselves better, and it shows in the pricing. Intel now wants to take away one of its opponents' key advantages: building chips from the ground up alongside target clients, effectively getting ASICs with minimal latency attached to their CPUs, also saving on power and heat. With Intel going fully custom in the server market, we could see a shift in the balance of power between Intel, IBM, and Oracle that hasn't been felt since the original HPC war. Overall IBM and Oracle have very little marketshare, but in the areas where they dominate, it's practically a 50/50 split between the two at very high margins. It'll be interesting to see if Intel can break into IBM's last stronghold after many years of leaving Big Blue with the financial sector. I wonder if Intel would be willing to collaborate with AMD and put Fiji/Greenland onto future Broadwell EP/EX and Skylake EP/EX. It seems like a good way to keep AMD alive while still taking most of the immediate financial benefit. Hell, maybe Intel will work with Nvidia and create CUDA-based APUs for some in the scientific computing arena as old systems need to be upgraded to attract new customers. And as a far-fetched nonsense idea, what if this foreshadows Intel eventually going after AMD's console business 5-7 years down the road?

Here's my original posting in the Peripherals section: http://linustechtips.com/main/topic/28705-mojo-audio-visualizer-clock-by-embeddedmicro-w-pics/, but I figure this thing is worthy of a custom metal/plexiglass enclosure. Here's some pics of the front-face (the rear will be mirror of the front, with some modification to fit the Mojo FPGA board). I used Google's SketchUp (which was surprisingly easy). Some of the measurements are a bit off but it gives me an idea for the metal fab...everything else (plexiglass) should fall into place :D

Here's a cool project I'd though I'd share...it's a dual function Clock / Audio Visualizer based on a Spartan 6 FPGA (Field-Programmable Gate Array) made by EmbeddedMicro via their Kickstarter campaign. You can check out the hardware, and more importantly, the growing list of tutorials to help the beginner (like me! :D). You can see the prototype device in action here: . The retail version functions the same, but also looks BA with a matte black PCB and green accents. It also goes PERFECTLY with Logan's (@Teksyndicate; http://zweihander.bandcamp.com/) Zweihander 8bit music! It's almost as if they were made for each other. I'll attach some pics here and will soon post design plans (in the New Builds & Planning section?) for a metal/plexiglass enclosure to show it off properly. If I do a PC build, it may go in a 5.25" bay too (the 8x16 LED display in 4.75" wide, and its PCB is 5.5" wide). It wasn't cheap, but for some custom hardware and the tools/resources/tutorials to learn and play with it makes it an awesome little project, let me know what you think!