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Interview With AMD's Desktop Processor Marketing Manager, Don Woligroski

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15 hours ago, Tomsen said:

They had that since steamroller.

No they didn't. They made a split L1 cache for instructions/data.

 

 

Software Engineer for Suncorp (Australia), Computer Tech Enthusiast, Miami University Graduate, Nerd

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10 hours ago, patrickjp93 said:

No they didn't. They made a split L1 cache for instructions/data.

They did add a micro-uop queue that can shutdown the fetch + decode units if the decoded micro-oups are in place (aka similar function to a micro-uop cache, very much similar to Intels sandy implementation in functionality).

Please avoid feeding the argumentative narcissistic academic monkey.

"the last 20 percent – going from demo to production-worthy algorithm – is both hard and is time-consuming. The last 20 percent is what separates the men from the boys" - Mobileye CEO

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2 hours ago, Tomsen said:

They did add a micro-uop queue that can shutdown the fetch + decode units if the decoded micro-oups are in place (aka similar function to a micro-uop cache, very much similar to Intels sandy implementation in functionality).

Well according to Zen's tech slides, apparently not.

Software Engineer for Suncorp (Australia), Computer Tech Enthusiast, Miami University Graduate, Nerd

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20 minutes ago, patrickjp93 said:

Well according to Zen's tech slides, apparently not.

Which slides has any mention of zen micro oup cache specifically? Haven't seen one yet.

Also, it is not because tech sites haven't covered this with steamroller.

Please avoid feeding the argumentative narcissistic academic monkey.

"the last 20 percent – going from demo to production-worthy algorithm – is both hard and is time-consuming. The last 20 percent is what separates the men from the boys" - Mobileye CEO

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