PCIe lanes
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Solved by Bubben,
To answer my own question with the z77 chipset as an example.
There're a total of 20 pci-e 3.0 lanes available, each with a bandwidth of 7,88Gbit/s in both directions. 16 of these lanes are dedicated to the 16x slots and connected directly to what use to be the 'Northbridge', but the northbridge is nowadays integrated directly with the cpu. The remaining 4 lanes are sent through the DMI (where the bandwidth is converted to pci-e 2.0 lanes?) to what more or less used to be the 'Southbridge' but is now more commonly referred to as the actual chipset. At the chipset the bandwidth is divided as needed in between remaining pci slots, sata and general I/O.
Or at least that's how I understood it, so don't necessarily take my word for it.

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