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7 minutes ago, BiotechBen said:

Would somebody be able to explain what this is to me? 😄

a pcie connection consists of one or more (up to sixteen, at the moment) data-transmission lanes, connected serially. Each lane consists of two pairs of wires, one for transmitting and one for receiving. There are 1, 4, 8 or 16 lanes in a single pcie slot – denoted as x1, x4, x8, or x16

 

keep it at x16 to use the maximum performance! - ( the image shows of how it is splitting up ), if you have many pcie ports, thats how they will be divided ) 

 

This will help you understand it better - Click Here

hey! i know to use a computer

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I'm confused at what the different options would do on my board....

 

So I have 2 16x slots, one is 16x electrically one is 4x and then 4 1x slots. The 1x are labelled at 2.0 speeds, with a 3.0 16x slot at full capacity, and an NVMe drive in M2_1 with 4 gen 3 links directly to CPU, would I be able to use the 1x slots without stealing bandwidth from the 16x slot? And are they enabled automatically? My understanding is that they are coming off the PCH? So I have 20 lanes with this CPU, 16 for gpu, 4 for NVMe and then the chipset also has lanes? Maybe I don't understand the math here put 20+anything is more than 20?

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