verilog help

[Matty2048]

hello,

 

I thought this was the best place to put this but idk.

 

I have a bcd to 7 segment display converter coded and a bcd counter but I'm struggling on how to link them together. 

 

-many thanks 

[Matty2048]

nevermind managed to do it

 

here's my code

module counter    (
   out     ,  // Output of the counter
  enable  ,  // enable for counter
  clk     ,  // clock Input
  reset   ,
seg   // reset Input
  );
  //----------Output Ports--------------
      output [3:0] out;
		output [7:1] seg;
 //------------Input Ports--------------
      input enable, clk, reset;
 //------------Internal Variables--------
      reg [3:0] out;
		reg [7:1] seg;
 //-------------Code Starts Here-------

 always @(posedge clk)
 begin
 if (out == 9)
	out <= 8'b0;

else if (reset) 
  out <= 8'b0 ;
 else if (enable)
    out <= out + 1;
end


always @*
begin 
case (out) 

/*makes stuff opt on seg
stuff on lhs is 'filter' for case using bcd
stuff on rhs is what outpts on seg outputs 
~ is used to invert the binary on rhs (makes it easier)
*/

4'b0000:seg=7'b0111111;
4'b0001:seg=7'b0000110;
4'b0010:seg=7'b1011011;
4'b0011:seg=7'b1001111;
4'b0100:seg=7'b1100110;
4'b0101:seg=7'b1101101;
4'b0110:seg=7'b1111101;
4'b0111:seg=7'b0000111;
4'b1000:seg=7'b1111111;
4'b1001:seg=7'b1101111;

default : seg= 7'b1111111;
endcase
end
  
  endmodule 
 

 

Edited October 28, 2018 by Matty2048
that other code was wrong

[CloroxBleach57]

What is this for, because it probably depends. For example, is this for arduino e.g. something that takes 7 segment inputs?

Edit: saw the top of your second post lol

[abdullah2993]

The seg should be the output...right?