SPI Interface VHDL

[Ovisss4]

Hi everyone,

 

so I quite liked digital logic class at the University and my lecturer noticed that and he gave me some extra stuff to do. So the first task was booth multiplier which I done. The new task as the title says is SPI interface. And while I searched on Internet i got confused how it works. So I understand the basics that Master and Slave has 4 pin connection( SCLK, MISO, MOSI, SS). But I have no idea what are the other connections, like how does it receive and transmit data which needs to be shifted, when I does load data.And most important about I have no clue how Buffer work. First I thought that it stores extra data so that that processor could prepare another data, but then found that there is some sort of FiFo Buffer which I'm still trying to understand how it works. And about Serial clock generator(divider) how much it should be able to divide clock signal. So if someone could answer any of these question I would be very thankful