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It might be a little early for this question but I had a question about DDR5. I was doing a little research about it I found that each DIMM has two channels. So what we currently understand as dual channel is now accomplished using 1 DIMM? Does that possibly mean future builds using DDR5 would be built with only 1 DIMM? Quad channel would be accomplished using a dual DIMM module kit, similar to what we use now to get dual channel? When building a system I've always used two DIMMs so I get dual channel, I assume most people do the same to get the most performance. Would quad channel take dual channels place as the default design when building a new computer?

 

This all sounds very cool, but looks like there is a lot to learn about this new memory and maybe some questions won't be answered until we can get our hands on it.

 

DIMM-DDR5.png

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11 minutes ago, Noxz86 said:

It might be a little early for this question but I had a question about DDR5. I was doing a little research about it I found that each DIMM has two channels. So what we currently understand as dual channel is now accomplished using 1 DIMM? Does that possibly mean future builds using DDR5 would be built with only 1 DIMM? Quad channel would be accomplished using a dual DIMM module kit, similar to what we use now to get dual channel? When building a system I've always used two DIMMs so I get dual channel, I assume most people do the same to get the most performance. Would quad channel take dual channels place as the default design when building a new computer?

 

This all sounds very cool, but looks like there is a lot to learn about this new memory and maybe some questions won't be answered until we can get our hands on it.

Depends entirely on how the CPU manufacturers choose to implement the memory controllers. It's too early to speculate.

Main: AMD Ryzen 7 5800X3D, Nvidia GTX 1080 Ti, 16 GB 4400 MHz DDR4 Linux - Fedora

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Yes, there's 2 channels, but it's not quite the equivalent of old dual channel

DDR4 is 64 bit wide, dual channel means opportunity to read/write 2 x 64 bit.

 

The new DDR5 is 40bit per channel (you can easily see from the picture , 5 chips x 8 bit = 40 bits) and i don't know if a part of these bits is ECC information or not (didn't do my research, and I heard the DDR5 has some built in error correction by default, so not sure how it works)

 

I suspect one one of the reasons why they did it like this is because  bigger capacities per chip and to save power by disabling one channel when needed.

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