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CarlBar

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About CarlBar

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  1. CarlBar

    Intel Comet Lake Packs Up to 10 Cores

    At no point in the quoted discussion does he talk about a 20 core part. Try again. Q2 2017 was also when AMD launched the Ryzen 5 2600x. By the time these CPU's arrive we should be in the process of getting the R6 3600X which by all indications will be matching a 9900K, using user benchmarks comparison as a basis, (it;s quick and easy to dig up ok), thats a more than 30% improvement in performance in 2 years. Conversely nothing we've heard so far suggest this 10 core will have more than a few percent edge over the equally old 7900X, (i'd guesstimate 10-15% myself), and it will be a well over 100w part whilst AMD are claiming near parity on TDP with their new part given what they showed off at CES. Thats another strike against intel. The new 10 core may have a huge edge over the then top of the line desktop processor just from all those extra cores, but it's seeing a huge power usage spike. Which means intel is basically brute forcing things. if we can criticize AMD for doing that with Vega and NVIDIA for Firmi (to name 2 other examples), i don't see why we can't do the sanme here. The only, (and highly arguable), innovation here is that intel has managed to get process yields to the point they can yield such a chip at a commercially viable price point and quantity. But that kind of improving yield is par for the course with process nodes hence why i say it's arguable.
  2. At no point did i say boeing where unaware of the problem, the point i'm trying to make that your ignoring, (as you seem to anything in any argument that undermines your position), is that fixing it may and probably would require significant redesign work. Weather thats worth it or necessary is a complex calculation based on some of those factors i mentioned. https://en.wikipedia.org/wiki/Lion_Air_Flight_610#Previous_flight_problems Turns out it was a pilot on the ground that walked them through disabling. As for what happens when the bandaid falls off. What almost allways happens when an automated flight control system malfunctions and the pilots are unable to disable it. The aircraft crashes. This isn't unique to the MACS system, most of the automated flight systems can and will cause this. The issue appears to be that unlike prior automatic systems no one adequately briefed the pilots on the necessary info to recognise and cope with a MACS problem.
  3. CarlBar

    Intel Comet Lake Packs Up to 10 Cores

    The entire discussion chain leading up to my post, 9the next post made in this was the one i initially quoted. You keep replying to someone saying this is not revolutionary by pointing out intel hasn't had a 10 core part at high clocks before. Then someone points out they have. What am i expecting you to understand that you haven't explicitly stated. I can only assume you completely failed to understand what @The Benjamins was arguing in the first place...
  4. This, 99% of required safety features on anything you use from a dishwasher to a multi-million dollar aircraft are the result of unexpected tings happening and authorities realising there's an issue and regulating them into place. Look below. They read their manuals. The first of these two crashes occurred because pilots aren't adequately briefed on how to cope with a malfunctioning MACS. But the procedures where in their SOP manual. The Airline just didn't emphasize that aspect of things much in training sessions. The aircraft that went down in the first accident actually had an identical problem on it's previous flight but the pilots where able to cope. Your clearly clueless about aero/fluid dynamics. I don't have the depth of knowledge i'd like there but it's a sufficiently major area of interest for me that i've put a lot of effort into reading up on it over the years and quite small changes can produce large effects. In this case it's likely they couldn't fix the issues without so significantly redesigning the aircraft that they'd functionally be designing an all new one. Bear in mind most large airliners have a lot of different automatic control systems designed to fly the plane through all kinds of complex situations. For that matter military aircraft have been using systems of a similar purpose for decades without issue in the overwhelming majority of cases. The F-16 was the first aircraft setup that way as a production model AFAIK. Having to rely at least partially on an automatic system to fly the plane if you don't have absolute grade A++~ flight crew is pretty normal. Thats why any major systems malfunction usually results in the flight diverting. The pilots might be able to cope but it's allways considered safer to get them down now in case more systems fail to the point the pilots can't cope.
  5. CarlBar

    Ryzen 3000 „Valhalla“

    Yeah the plan for AMD is to be on 5nm at Zen 4 if i recall the rome launch event slides correct. There's really no reason they'd ever be on a high yielding node long enough for that theroy to make sense unless they find themselves in the same kind of situation intel is in with 10nm ATM.
  6. CarlBar

    Leaked Intel GPU Shroud Designs

    Lol. Intel does not have the node for that. I'm still super interested to see what they do. Also leads to the potentially amusing idea of running an AMD CPU with an Intel GPU. That makes a lot more sense...
  7. CarlBar

    Ryzen 3000 „Valhalla“

    Ahhh thank you. I doubt it on putting IO on the chiplets. The entire point of going to a chiplet architecture is to get all the stuff that doesn't benefit from a smaller process node off said nod and leave it on an older higher yielding node whilst leaving the stuff that does benefit on the new node but spread amongst several smaller chips, (which improves yields).
  8. CarlBar

    Ryzen 3000 „Valhalla“

    Yeha but that relies on interconnects between ccx's, (or in the case chiplets), which we know rome doesn't have, (Ryzen/TR will apparently but i'd assume memory copies rome), so they can't be doing it that way because the only thing it can hop through is the IO die, it makes no sense to hop to the IO die to hop to another chiplet to hop back to the IO die to hop to the memory. I also want to say i remember them saying NUMA is dead but i can't remember for 100% sure.
  9. CarlBar

    Ryzen 3000 „Valhalla“

    Oh sure, but i was addressing the questions about weather one chiplets might not be able to access a given memory channel at all. besides major screw ups aside the hugely increased frequancy of the IF links should shave a fair amount off the latency all by itself as it spends less time in hop that way.
  10. CarlBar

    Ryzen 3000 „Valhalla“

    No offence, (seriously), mr sheep but i think you left your brain in neutral. AMD demo'd an 8 core at CES, it only had the same TDP, (65w), as the existing Ryzen 5. So long as the B series motherboards can handle current R7's they probably can cope with the new R7'sn where going to get. though making any hard plans would be inadvisable. Also super dumb question, got a tiachi ultimate MB, how do i check/do the bios update, (i haven't messed with a bios update since before UEFI was a thing)? Probably not going to be able to justify grabbing a 3000 series out the door but might as well make sure it's sorted next time i reboot.
  11. CarlBar

    Ryzen 3000 „Valhalla“

    AMD explicitly said for rome at least that any single chiplet can if it absolutely needs to call on the full memory bandwidth of every memory channel on the IO die, (8 channels at 32000mhz or just over 200GB/s). I'd assume the same holds true of Ryzen so it probably is a preferred memory channel thing.
  12. CarlBar

    Nvidia Brings DXR Raytracing to Pascal, Turing and Volta

    What i said is that it's a different but related technique ;). They're similar but have some key differences. Also i linked the video because it's clear he went to a lot of effort researching it, (TLDR thats basically how it got to be sponsored. he was doing the research and a company gave him a load of stuff and said "we don't mind giving this for free" but he felt he owed them a bit more exposure for the help so he turned it into a sponsored video to reward the help with research they gave him. he talks about it towards the end of the video),
  13. I think all the discussion misses somthing. Where's the D15A? If they've improved the single fin stack design this much couldn't they do the same for the dual fin stack designs as well.
  14. CarlBar

    Intel Comet Lake Packs Up to 10 Cores

    And again what does any of that have to do with what's being discussed, (how revolutionary the technology being demonstrated in a high clock 10 core part is)? You seem to be arguing a completely different point here to the one i was replying to in the first place.
  15. CarlBar

    Experiences with non-techies

    That made sense. Owowowowowow. Also the fact that it has to pull all the data immediately is downright dumb.
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