Questions about Vram?

[Nielips]

So this is just purely out of curiosity. I want to know the answer to a few questions/clarify what I have read/heard. 

 

1) Would I be write in saying that the bandwidth of GDDR doesn't increase from each successive generation? it just increase by increasing the amount of traces on the PCB?

 

2) As smaller manufacturing processes are utilised does the size of the VRAM not decrease as well? If it was the case that it did, could you not just increase the amount on the PCB instead of implementing a costly new VRAM architecture. 

 

3) What are the main differences between the upcoming new architecture and GDDR?

 

I don't mind going and reading other websites, if people don't have the time to explain it, I would just like to understand.

 

Thanks

[Cheddle]

im a noob, but, a simple explanation:

 

1)

GDDR5 does 4 data transfers per clock cycle, as such its "quad" data rate memory. its bandwidth can be increased by upping its "mhz" aka "millions of cycles per second". the data in these chips is read in 64-bit "chunks" - a gpu can access multiple chips at once by reading from more than one ram chip, this is how you achieve a memory bus of "256-bit" (4-chips at once) or "512-bit" (8-chips at once) - this means the gpu can access multiple chips at once, kind of like SLI for your ram chips.

 

This means that the effective "speed" of the memory is "bus-width"x"effective clock" = "bits-per-second" - i.e my gtx980 has an effective clock of 8,000mhz (2,000mhz of GDDR5) and it has a 256-bit bus - 256x8000=2,048,000 million bits/s / 8 = 256,000 million bytes/s / 1000 = 256 gb/s

 

so now that we know how the memory "speed" is increased... we can see we can either, access more ram chips at once (r9 290 has 512-bit bus for example), increase the mhz of the ram,

 

Alternativley develop new chips than can be be read in higher than 64-bit chunks per transfer, or increase the number of transfers per cycle... This means redeveloping the whole architecture of the ram.

 

2)

Memory chips are not manufactured on the same "die-size" as gpu/cpus - gddr5 is about 46nm in production where as current GPU/CPU's are on about 20nm - this is more about cost cutting and high-yeild productions then trying to cram as much ram into a small a die as possible. as the processes for making 20nm and smaller chips result in many defective chips that are useless.

 

It makes more sense to cram more individual ram chips onto a pcb than it does to make more ram fit inside a chip - for the above explained reasons of bus width

 

3) 

Enter HBM - high-bandwidth memory - the next step from GDDR5 - I am not really sure how this works but this is my understanding so correct me if I am wrong

 

Memory chips are packaged on top of each other, with 4 chips per stack,  each stack has 2 x 128-bit channels - so per chip 1024-bit's can be accessed per cycle, per chip stack. lets pretend its single-data-rate (not quad like gddr5), that we have four chips on a PCB and that its running at 1ghz effective clock

 

(4x1024)*1000 = 4,096,000 million bit/s / 8 = 512,000 million bytes/s = 512 gb/s 

 

So with just four ram chips on a pcb, running at half the speed of GDDR5 we have approximately double the memory bandwidth that GDDR5 provides - you could say its four times as fast cycle for cycle.

[D2ultima]

So this is just purely out of curiosity. I want to know the answer to a few questions/clarify what I have read/heard. 

 

1) Would I be write in saying that the bandwidth of GDDR doesn't increase from each successive generation? it just increase by increasing the amount of traces on the PCB?

 

2) As smaller manufacturing processes are utilised does the size of the VRAM not decrease as well? If it was the case that it did, could you not just increase the amount on the PCB instead of implementing a costly new VRAM architecture. 

 

3) What are the main differences between the upcoming new architecture and GDDR?

 

I don't mind going and reading other websites, if people don't have the time to explain it, I would just like to understand.

 

Thanks

1 - Bandwidth is dependent on the memory bus * the clock speed * any multiplications on the type of memory / 8, with GDDR3 being a 2x multiplier, and GDDR5 being a 4x multiplier. It does not need to increase with each successive generation, and memory bandwidth is not something many games care greatly about.

 

2 - vRAM I believe (though I could be wrong) is its own thing. They are attached to the memory controllers of the GPU, and the GPU's architecture and size have nothing to do with the actual size of the vRAM chips. It's like how RAM is the same size mostly, though CPUs keep getting smaller and smaller.

 

3 - I wish I could tell you. Apparently it is going to be using 3D memory (where memory is stacked on top of one another, or some such thing; I don't know much) which will allow for much higher sizes and connections while keeping the footprint on the layout very similar to how it currently is with GDDR5. But I'm probably totally wrong about this. I think the user above me has it more down pat.