64-bit only instruction CPU?

[MC.Morrado]

I was wondering how efficient modern X86-64 CPU's can be if all the old legacy junk and microcode was removed. How would a traditional X86 desktop CPU be different if it was optimized to only have 64-bit instructions instead of accumulating more instructions and bloated legacy junk normies won't even use on new hardware?

[eece_ret]

https://arstechnica.com/civis/threads/intel-wants-feeback-for-a-proposed-64-bit-only-cpu-architecture-called-x86s.1492146/

[GOTSpectrum]

I don't think you understand how CPUs work... 

CPUs do maths in 8, 18, 32, 64 bit... They also do it in 256 and 512bit with instructions like AVX. You use different register sizes for different instructions based on what the software needs. Many CPUs can "break down" these larger instruction to do multiple smaller instruction, like running 2 AVX 2 instructions on the AVX512 unit at the same time 

[porina]

Probably make less difference than you think in performance terms, maybe some savings in otherwise little used silicon. Intel have been working at it for some time now. https://www.intel.com/content/www/us/en/developer/articles/technical/envisioning-future-simplified-architecture.html

[MC.Morrado]

Disclaimer: I may be slightly stupid. Please tell me more about X86 instructions.

[starsmine]

1 hour ago, MC.Morrado said:

I was wondering how efficient modern X86-64 CPU's can be if all the old legacy junk and microcode was removed. How would a traditional X86 desktop CPU be different if it was optimized to only have 64-bit instructions instead of accumulating more instructions and bloated legacy junk normies won't even use on new hardware?

 

1 hour ago, MC.Morrado said:

Disclaimer: I may be slightly stupid. Please tell me more about X86 instructions.

I was about to say, Im not sure what question you are asking. 

x86 from day one, instructions were variable length. This means more work for the compiler and control logic, but it means more compact instruction sizes, meaning you can fit more instructions in a given instruction cache. SRAM was and still is, expensive.

What makes it 8/16/32/64/other bits is the bus widths/memory addressing. 

you can control how much data you grab from the registers by choosing different sized registers
Register AX is 16 bit. but you can grab the high or low by saying I want AH or AL
EAX is that same register, but 32 wide
RAX is the same register but 64 wide

The point more here is that the 16/32 bit parts are not necessarily taking up large amounts of space, as the 64 bit is using the same parts, but just wider.

Indieness may be wrong here, I dont want to think about indieness, it doesnt matter in terms of the concept, it does mater in terms of if al is on the far right or far left.

SIMD and AVX have access to MMX/XMM/YMM registers that are 64/128/256bit wide respectivly. (Remeber MMX came out on 32 bit processors)