9850x3d 1 cache only?

[Dreg]

Most current rumors point to having the 9850x3d with 1 cache for both CCDs... I will still wait to see if it affects gaming like the previous gens, but its looking like the 9800x3d might be the better pick here. 

 

Thoughts? 

[PDifolco]

I've rather heard the 9950X3D will have 2 x3D CCDs - which is possible/easier with the cache below the CPU now, but we'll see...

[Ebony Falcon]

Rummers in both directions 

some say both dies some say 1 

[Dreg]

My line of thought: even if its 2 caches, the 9850x3d (or 9950x3d) will surely run warmer (close to 9950x temps?), and the current 9950x temps are not the most pleasant from what I can see. 

 

The 9800x3d might be powerful enough for most workload tasks already. 

[starsmine]

13 hours ago, Dreg said:

My line of thought: even if its 2 caches, the 9850x3d (or 9950x3d) will surely run warmer (close to 9950x temps?), and the current 9950x temps are not the most pleasant from what I can see. 

 

The 9800x3d might be powerful enough for most workload tasks already. 

im confused by both of these claims.

9950x temps are very pleasent. 

9950x3d being compute die on top means not much difference in temp that we saw.

[Dreg]

3 hours ago, starsmine said:

im confused by both of these claims.

9950x temps are very pleasent. 

9950x3d being compute die on top means not much difference in temp that we saw.

Whats the idle temps for the 9950x, and under Cinebench? The ones I saw on reviews are pretty high, but I dont have one to test and confirm

[Haswellx86]

Ok, wtf is a 9850x3D? It is a 9950X3D.

 

Early rumors suggested that the 9950X3D would come with 3D V-Cache on both the CCDs, but now I think it's confirmed that only one CCD is getting the 3D V-Cache die.

 

I do want to state that what a lot of people get wrong that about this is that they are disappointed. You shouldn't really be.

 

It doesn't make a lot of sense to put 3D V-Cache on both the CCDs. In gaming, you already want to only have one CCD active for that game. If you have 3D V-Cache on both the CCDs, you will still run into the massive latency issue, and I think that it will be worse if one CCD has to gather data from the other CCD's 3D V-Cache, but I am not sure if that is how it works.

 

A lot of people blame the weird problem with the 7950X3D to be the 3D V-Cache being only on one CCD. Even if both of them had the 3D V-Cache, you would still only want to have one CCD active.

 

So basically, all your background stuff would be running on your other non 3D V-Cache CCD. They won't benefit much with 3D V-Cache.

 

And when it comes to multi-threaded workload, it could probably be better to not have 3D V-Cache (except some workloads which prefer faster memory than clocks, like AI/ML, but aren't you using GPUs for them?)  which could probably make them turbo higher. This was a much bigger problem on the 7950X3D, as with its heterogeneous design, the turbo behavior was different of both the CCDs in that the 3D V-Cache CCD would generally turbo lower than the one without it. This was because the 3D V-Cache die was constructed upon the CCD, which meant that a lot of the heat from the CCD would be trapped inside, and so the cooling the chip would be harder. That is why there were so delicate with voltage and overclocking was disabled. But now in Zen 5, the 3D V-Cache die is constructed on the bottom of the CCD, which means cooling the CCD is much easier and so overclocking is unlocked now. But still because of lesser complexity without the 3D V-Cache, the non 3D V-Cache die might be able to turbo more or overclock more.

 

All this, with the really high price increase by putting 3D V-Cache on both the CCDs, means their margins would be even lower.

[starsmine]

2 hours ago, Dreg said:

Whats the idle temps for the 9950x, and under Cinebench? The ones I saw on reviews are pretty high, but I dont have one to test and confirm

who cares about idle temps. turn your fans off and have it be silent in the 80s. 
hell who even cares about load temps. 

What makes a part toasty or not is not its temp anyways, its how many watts its putting out. 

[Dreg]

22 hours ago, Haswellx86 said:

Ok, wtf is a 9850x3D? It is a 9950X3D.

 

Early rumors suggested that the 9950X3D would come with 3D V-Cache on both the CCDs, but now I think it's confirmed that only one CCD is getting the 3D V-Cache die.

 

I do want to state that what a lot of people get wrong that about this is that they are disappointed. You shouldn't really be.

 

It doesn't make a lot of sense to put 3D V-Cache on both the CCDs. In gaming, you already want to only have one CCD active for that game. If you have 3D V-Cache on both the CCDs, you will still run into the massive latency issue, and I think that it will be worse if one CCD has to gather data from the other CCD's 3D V-Cache, but I am not sure if that is how it works.

 

A lot of people blame the weird problem with the 7950X3D to be the 3D V-Cache being only on one CCD. Even if both of them had the 3D V-Cache, you would still only want to have one CCD active.

 

So basically, all your background stuff would be running on your other non 3D V-Cache CCD. They won't benefit much with 3D V-Cache.

 

And when it comes to multi-threaded workload, it could probably be better to not have 3D V-Cache (except some workloads which prefer faster memory than clocks, like AI/ML, but aren't you using GPUs for them?)  which could probably make them turbo higher. This was a much bigger problem on the 7950X3D, as with its heterogeneous design, the turbo behavior was different of both the CCDs in that the 3D V-Cache CCD would generally turbo lower than the one without it. This was because the 3D V-Cache die was constructed upon the CCD, which meant that a lot of the heat from the CCD would be trapped inside, and so the cooling the chip would be harder. That is why there were so delicate with voltage and overclocking was disabled. But now in Zen 5, the 3D V-Cache die is constructed on the bottom of the CCD, which means cooling the CCD is much easier and so overclocking is unlocked now. But still because of lesser complexity without the 3D V-Cache, the non 3D V-Cache die might be able to turbo more or overclock more.

 

All this, with the really high price increase by putting 3D V-Cache on both the CCDs, means their margins would be even lower.

Maybe what they should do is actually sharing the same, perhaps bigger, 3D V-cache across both CCDs, so regarless which thread is being used, it is using that 1 cache. Just like a network shared drive of sorts. Manye games do actually use more than 8 cores, because they distribute the load on more cores. It is better than overloading specific cores, because that would raise the temps on those cores. 

[GreenLeaf]

first, WTF IS A 9850X3D????????

[Haswellx86]

21 minutes ago, Dreg said:

Maybe what they should do is actually sharing the same, perhaps bigger, 3D V-cache across both CCDs, so regarless which thread is being used, it is using that 1 cache. Just like a network shared drive of sorts. Manye games do actually use more than 8 cores, because they distribute the load on more cores. It is better than overloading specific cores, because that would raise the temps on those cores. 

I don't think that is easily possible. They use chiplets, modular and independent of each other. If they were to share the cache among each other, the both the CCDs and the 3D V-Cache would have to be constructed at the same instead of being modular or independent.

 

Also, sharing the 3D V-Cache means there has to be core to core communication to maintain cache coherency. Both CCDs as of now can't communicate with each other directly. One CCD has to talk to the IO die, which sends the request to the other CCD. Upon that, unlike Intel, AMD doesn't use a silicon interposer, and instead, routes the signals directly through the PCB, which increases latency significantly.

[Dreg]

53 minutes ago, Haswellx86 said:

I don't think that is easily possible. They use chiplets, modular and independent of each other. If they were to share the cache among each other, the both the CCDs and the 3D V-Cache would have to be constructed at the same instead of being modular or independent.

 

Also, sharing the 3D V-Cache means there has to be core to core communication to maintain cache coherency. Both CCDs as of now can't communicate with each other directly. One CCD has to talk to the IO die, which sends the request to the other CCD. Upon that, unlike Intel, AMD doesn't use a silicon interposer, and instead, routes the signals directly through the PCB, which increases latency significantly.

Would not that mean for gaming, using 2 CCDs will never be efficient or with low-latency as just using 8cores only? Thats regardless of V-Cache

[Haswellx86]

29 minutes ago, Dreg said:

Would not that mean for gaming, using 2 CCDs will never be efficient or with low-latency as just using 8cores only? Thats regardless of V-Cache

I don't understand what you are trying to say.

 

Yes, only using 8 cores in one CCD is better than 16 cores between 2 CCDs for gaming, and I think even with the 3D V-Cache, it would be better to run on single CCD instead of communicating between two heterogeneous CCDs (one with 3D V-Cache and one without).

[Dreg]

1 hour ago, Haswellx86 said:

I don't understand what you are trying to say.

 

Yes, only using 8 cores in one CCD is better than 16 cores between 2 CCDs for gaming, and I think even with the 3D V-Cache, it would be better to run on single CCD instead of communicating between two heterogeneous CCDs (one with 3D V-Cache and one without).

Ya thats what I meant. 1 CCD will always be better for pure gaming than having 2 CCDs, regardless if there is 1 V-cache, or 2. 

 

How is the 9950x right now with games? Is scheduling good enough to run all games on first CCD, or we still need lasso, etc?

[Haswellx86]

12 minutes ago, Dreg said:

How is the 9950x right now with games? Is scheduling good enough to run all games on first CCD, or we still need lasso, etc?

I think the scheduling itself when works has been working correctly, but all the fuss right is that it is not straightforward to get it working.

 

The inter-CCD latency problem has been there since the birth of Ryzen, but nobody really noticed it, until its effects started to get more obvious as AMD processors got faster (LTT still used to show the problem in Zen 2 and Zen 3 era, but it wasn't that obvious), and especially when the single CCD X3D processors were faster than a dual CCD ones.

 

I think in Ryzen 7000, they added the scheduling. But getting it working has been a hassle for everyone. Go watch this video. With the term Wintel it is, I have no idea why Microsoft isn't integrating this in the kernel itself. Linux on the other hand I think has decent support for core parking.

 

Benchmarkers with a dual chiplet, especially X3D chips just disable the other CCD.

[Bagzie]

On 11/28/2024 at 9:45 PM, PDifolco said:

I've rather heard the 9950X3D will have 2 x3D CCDs - which is possible/easier with the cache below the CPU now, but we'll see...

Question is will it make any difference? I would think definitely not for games since as soon as you introduce the ccd to ccd latency penalty any gains made by two ccd's will be wiped out but i guess there's some productivity workloads that will benefit.

[PDifolco]

58 minutes ago, Bagzie said:

Question is will it make any difference? I would think definitely not for games since as soon as you introduce the ccd to ccd latency penalty any gains made by two ccd's will be wiped out but i guess there's some productivity workloads that will benefit.

Agreed, but having the same "layout" on the 2 CCD will make things like voltage control, power management, and overclocking easier, and games will have less of a drop compared to switching to a non x3D core

[Dreg]

Maybe the 2 CCDs architecture will haunt AMD for a long time, especially for gaming. Intel CPUs are actually better in this regard, its excellent for gaming and workloads, with no real compromise (except temps and power).